binutils/

* doc/binutils.texi (objdump): Document -Mppcps.

gas/
	* config/tc-ppc.c (parse_cpu): Handle "750cl".
	(pre_defined_registers): Add "gqr0" to "gqr7", "gqr.0" to "gqr.7".
	(md_show_usage): Document -m750cl.
	(md_assemble): Handle two delimiters in succession (eg. `),').
	* doc/c-ppc.texi (PowerPC-Opts): Document -m750cl.
	* testsuite/gas/ppc/ppc.exp: Run ppc70ps dump tests.
	* testsuite/gas/ppc/ppc750ps.s: New file.
	* testsuite/gas/ppc/ppc750ps.d: Likewise.

include/opcode/
	* ppc.h (PPC_OPCODE_PPCPS): New.

opcodes/
	* ppc-opc.c (PSW, PSWM, PSQ, PSQM, PSD, MTMSRD_L): New.
	(XOPS, XOPS_MASK, XW, XW_MASK): Likewise.
	(PPCPS): Likewise.
	(powerpc_opcodes): Add all pair singles instructions.
	* ppc-dis.c (powerpc_dialect): Handle "ppcps".
	(print_ppc_disassembler_options): Document -Mppcps.

binutils/ChangeLog

@@ -1,3 +1,7 @@
+2007-08-22  Ben Elliston  <bje@au.ibm.com>
+
+	* doc/binutils.texi (objdump): Document -Mppcps.
+
 2007-08-17  Alan Modra  <amodra@bigpond.net.au>
 
 	* po/Make-in: Add --msgid-bugs-address to xgettext invocation.

binutils/doc/binutils.texi

@@ -1819,9 +1819,10 @@ suffix could be inferred by the operands.
 
 For PPC, @option{booke}, @option{booke32} and @option{booke64} select
 disassembly of BookE instructions.  @option{32} and @option{64} select
-PowerPC and PowerPC64 disassembly, respectively.  @option{e300} selects
+PowerPC and PowerPC64 disassembly, respectively.  @option{e300}
-disassembly for the e300 family.  @option{440} selects disassembly for
+selects disassembly for the e300 family.  @option{440} selects
-the PowerPC 440.
+disassembly for the PowerPC 440.  @option{ppcps} selects disassembly
+for the paired single instructions of the PPC750CL.
 
 For MIPS, this option controls the printing of instruction mnemonic
 names and register names in disassembled instructions.  Multiple

gas/ChangeLog

@@ -1,3 +1,14 @@
+2007-08-23  Ben Elliston  <bje@au.ibm.com>
+
+	* config/tc-ppc.c (parse_cpu): Handle "750cl".
+	(pre_defined_registers): Add "gqr0" to "gqr7", "gqr.0" to "gqr.7".
+	(md_show_usage): Document -m750cl.
+	(md_assemble): Handle two delimiters in succession (eg. `),').
+	* doc/c-ppc.texi (PowerPC-Opts): Document -m750cl.
+	* testsuite/gas/ppc/ppc.exp: Run ppc70ps dump tests.
+	* testsuite/gas/ppc/ppc750ps.s: New file.
+	* testsuite/gas/ppc/ppc750ps.d: Likewise.
+
 2007-08-23  Ben Elliston  <bje@au.ibm.com>
 
 	* doc/c-arm.texi (ARM Directives): Move brackets out of @vars.

gas/config/tc-ppc.c

@@ -396,6 +396,24 @@ static const struct pd_reg pre_defined_registers[] =
 
   { "fpscr", 0 },
 
+  /* Quantization registers used with pair single instructions.  */
+  { "gqr.0", 0 },
+  { "gqr.1", 1 },
+  { "gqr.2", 2 },
+  { "gqr.3", 3 },
+  { "gqr.4", 4 },
+  { "gqr.5", 5 },
+  { "gqr.6", 6 },
+  { "gqr.7", 7 },
+  { "gqr0", 0 },
+  { "gqr1", 1 },
+  { "gqr2", 2 },
+  { "gqr3", 3 },
+  { "gqr4", 4 },
+  { "gqr5", 5 },
+  { "gqr6", 6 },
+  { "gqr7", 7 },
+
   { "lr", 8 },     /* Link Register */
 
   { "pmr", 0 },
@@ -824,6 +842,9 @@ parse_cpu (const char *arg)
 	   || strcmp (arg, "603") == 0
 	   || strcmp (arg, "604") == 0)
     ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32;
+  /* Do all PPC750s have paired single ops?  */
+  else if (strcmp (arg, "750cl") == 0)
+    ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_PPCPS;
   /* -m403 and -m405 mean to assemble for the PowerPC 403/405.  */
   else if (strcmp (arg, "403") == 0
 	   || strcmp (arg, "405") == 0)
@@ -1091,7 +1112,8 @@ PowerPC options:\n\
 -m403, -m405		generate code for PowerPC 403/405\n\
 -m440			generate code for PowerPC 440\n\
 -m7400, -m7410, -m7450, -m7455\n\
-			generate code For PowerPC 7400/7410/7450/7455\n"));
+			generate code for PowerPC 7400/7410/7450/7455\n\
+-m750cl			generate code for PowerPC 750cl\n"));
   fprintf (stream, _("\
 -mppc64, -m620		generate code for PowerPC 620/625/630\n\
 -mppc64bridge		generate code for PowerPC 64, including bridge insns\n\
@@ -2639,6 +2661,14 @@ md_assemble (char *str)
 	{
 	  endc = ')';
 	  need_paren = 0;
+	  /* If expecting more operands, then we want to see "),".  */
+	  if (*str == endc && opindex_ptr[1] != 0)
+	    {
+	      do
+		++str;
+	      while (ISSPACE (*str));
+	      endc = ',';
+	    }
 	}
       else if ((operand->flags & PPC_OPERAND_PARENS) != 0)
 	{

gas/doc/c-ppc.texi

@@ -55,6 +55,9 @@ Generate code for PowerPC 440.  BookE and some 405 instructions.
 @item -m7400, -m7410, -m7450, -m7455
 Generate code for PowerPC 7400/7410/7450/7455.
 
+@item -m750cl
+Generate code for PowerPC 750CL.
+
 @item -mppc64, -m620
 Generate code for PowerPC 620/625/630.
 

gas/testsuite/gas/ppc/ppc.exp

@@ -41,5 +41,6 @@ if { [istarget powerpc*-*-*] } then {
 	run_dump_test "booke"
 	run_dump_test "e500"
 	run_list_test "range" "-a32"
+	run_dump_test "ppc750ps"
     }
 }

gas/testsuite/gas/ppc/ppc750ps.d

@@ -0,0 +1,72 @@
+#as: -m750cl
+#objdump: -dr -Mppcps
+#name: PPC750CL paired single tests
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+Disassembly of section \.text:
+
+0+0000000 <start>:
+   0:	e0 03 d0 04 	psq_l   f0,4\(r3\),1,5
+   4:	e4 22 30 08 	psq_lu  f1,8\(r2\),0,3
+   8:	10 45 25 4c 	psq_lux f2,r5,r4,1,2
+   c:	10 62 22 8c 	psq_lx  f3,r2,r4,0,5
+  10:	f0 62 30 08 	psq_st  f3,8\(r2\),0,3
+  14:	f4 62 70 08 	psq_stu f3,8\(r2\),0,7
+  18:	10 43 22 ce 	psq_stux f2,r3,r4,0,5
+  1c:	10 c7 46 0e 	psq_stx f6,r7,r8,1,4
+  20:	10 a0 3a 10 	ps_abs  f5,f7
+  24:	10 a0 3a 11 	ps_abs. f5,f7
+  28:	10 22 18 2a 	ps_add  f1,f2,f3
+  2c:	10 22 18 2b 	ps_add. f1,f2,f3
+  30:	11 82 20 40 	ps_cmpo0 cr3,f2,f4
+  34:	11 82 20 c0 	ps_cmpo1 cr3,f2,f4
+  38:	11 82 20 00 	ps_cmpu0 cr3,f2,f4
+  3c:	11 82 20 80 	ps_cmpu1 cr3,f2,f4
+  40:	10 44 30 24 	ps_div  f2,f4,f6
+  44:	10 44 30 25 	ps_div. f2,f4,f6
+  48:	10 01 18 ba 	ps_madd f0,f1,f2,f3
+  4c:	10 01 18 bb 	ps_madd. f0,f1,f2,f3
+  50:	10 22 20 dc 	ps_madds0 f1,f2,f3,f4
+  54:	10 22 20 dd 	ps_madds0. f1,f2,f3,f4
+  58:	10 22 20 de 	ps_madds1 f1,f2,f3,f4
+  5c:	10 22 20 df 	ps_madds1. f1,f2,f3,f4
+  60:	10 44 34 20 	ps_merge00 f2,f4,f6
+  64:	10 44 34 21 	ps_merge00. f2,f4,f6
+  68:	10 44 34 60 	ps_merge01 f2,f4,f6
+  6c:	10 44 34 61 	ps_merge01. f2,f4,f6
+  70:	10 44 34 a0 	ps_merge10 f2,f4,f6
+  74:	10 44 34 a1 	ps_merge10. f2,f4,f6
+  78:	10 44 34 e0 	ps_merge11 f2,f4,f6
+  7c:	10 44 34 e1 	ps_merge11. f2,f4,f6
+  80:	10 60 28 90 	ps_mr   f3,f5
+  84:	10 60 28 91 	ps_mr.  f3,f5
+  88:	10 44 41 b8 	ps_msub f2,f4,f6,f8
+  8c:	10 44 41 b9 	ps_msub. f2,f4,f6,f8
+  90:	10 43 01 72 	ps_mul  f2,f3,f5
+  94:	10 43 01 73 	ps_mul. f2,f3,f5
+  98:	10 64 01 d8 	ps_muls0 f3,f4,f7
+  9c:	10 64 01 d9 	ps_muls0. f3,f4,f7
+  a0:	10 64 01 da 	ps_muls1 f3,f4,f7
+  a4:	10 64 01 db 	ps_muls1. f3,f4,f7
+  a8:	10 20 29 10 	ps_nabs f1,f5
+  ac:	10 20 29 11 	ps_nabs. f1,f5
+  b0:	10 20 28 50 	ps_neg  f1,f5
+  b4:	10 20 28 51 	ps_neg. f1,f5
+  b8:	10 23 39 7e 	ps_nmadd f1,f3,f5,f7
+  bc:	10 23 39 7f 	ps_nmadd. f1,f3,f5,f7
+  c0:	10 23 39 7c 	ps_nmsub f1,f3,f5,f7
+  c4:	10 23 39 7d 	ps_nmsub. f1,f3,f5,f7
+  c8:	11 20 18 30 	ps_res  f9,f3
+  cc:	11 20 18 31 	ps_res. f9,f3
+  d0:	11 20 18 34 	ps_rsqrte f9,f3
+  d4:	11 20 18 35 	ps_rsqrte. f9,f3
+  d8:	10 22 20 ee 	ps_sel  f1,f2,f3,f4
+  dc:	10 22 20 ef 	ps_sel. f1,f2,f3,f4
+  e0:	10 ab 10 28 	ps_sub  f5,f11,f2
+  e4:	10 ab 10 29 	ps_sub. f5,f11,f2
+  e8:	10 45 52 54 	ps_sum0 f2,f5,f9,f10
+  ec:	10 45 52 55 	ps_sum0. f2,f5,f9,f10
+  f0:	10 45 52 56 	ps_sum1 f2,f5,f9,f10
+  f4:	10 45 52 57 	ps_sum1. f2,f5,f9,f10
+  f8:	10 03 2f ec 	dcbz_l  r3,r5

gas/testsuite/gas/ppc/ppc750ps.s

@@ -0,0 +1,66 @@
+# PowerPC 750 paired single precision tests
+	.section ".text"
+start:
+	psq_l	0, 4(3), 1, 5
+	psq_lu	1, 8(2), 0, 3
+	psq_lux	2, 5, 4, 1, 2
+	psq_lx	3, 2, 4, 0, 5
+	psq_st	3, 8(2), 0, 3
+	psq_stu	3, 8(2), 0, 7
+	psq_stux 2, 3, 4, 0, 5
+	psq_stx	6, 7, 8, 1, 4
+	ps_abs	5,7
+	ps_abs.	5,7
+	ps_add	1,2,3
+	ps_add. 1,2,3
+	ps_cmpo0 3,2,4
+	ps_cmpo1 3,2,4
+	ps_cmpu0 3,2,4
+	ps_cmpu1 3,2,4
+	ps_div 2,4,6
+	ps_div. 2,4,6
+	ps_madd 0,1,2,3
+	ps_madd. 0,1,2,3
+	ps_madds0 1,2,3,4
+	ps_madds0. 1,2,3,4
+	ps_madds1 1,2,3,4
+	ps_madds1. 1,2,3,4
+	ps_merge00 2,4,6
+	ps_merge00. 2,4,6
+	ps_merge01 2,4,6
+	ps_merge01. 2,4,6
+	ps_merge10 2,4,6
+	ps_merge10. 2,4,6
+	ps_merge11 2,4,6
+	ps_merge11. 2,4,6
+	ps_mr 3,5
+	ps_mr. 3,5
+	ps_msub 2,4,6,8
+	ps_msub. 2,4,6,8
+	ps_mul 2,3,5
+	ps_mul. 2,3,5
+	ps_muls0 3,4,7
+	ps_muls0. 3,4,7
+	ps_muls1 3,4,7
+	ps_muls1. 3,4,7
+	ps_nabs	1,5
+	ps_nabs. 1,5
+	ps_neg 1,5
+	ps_neg. 1,5
+	ps_nmadd 1,3,5,7
+	ps_nmadd. 1,3,5,7
+	ps_nmsub 1,3,5,7
+	ps_nmsub. 1,3,5,7
+	ps_res 9,3
+	ps_res. 9,3
+	ps_rsqrte 9,3
+	ps_rsqrte. 9,3
+	ps_sel 1,2,3,4
+	ps_sel. 1,2,3,4
+	ps_sub 5,11,2
+	ps_sub. 5,11,2
+	ps_sum0 2,5,9,10
+	ps_sum0. 2,5,9,10
+	ps_sum1 2,5,9,10
+	ps_sum1. 2,5,9,10
+	dcbz_l 3,5

include/opcode/ChangeLog

@@ -1,3 +1,7 @@
+2007-08-08  Ben Elliston  <bje@au.ibm.com>
+
+	* ppc.h (PPC_OPCODE_PPCPS): New.
+
 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 
 	* m68k.h: Document j K & E.

include/opcode/ppc.h

@@ -146,6 +146,9 @@ extern const int powerpc_num_opcodes;
 /* Opcode is only supported by PowerPC Cell family.  */
 #define PPC_OPCODE_CELL		 0x8000000
 
+/* Opcode is supported by CPUs with paired singles support.  */
+#define PPC_OPCODE_PPCPS	 0x10000000
+
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 

opcodes/ChangeLog

@@ -1,3 +1,12 @@
+2007-08-22  Ben Elliston  <bje@au.ibm.com>
+
+	* ppc-opc.c (PSW, PSWM, PSQ, PSQM, PSD, MTMSRD_L): New.
+	(XOPS, XOPS_MASK, XW, XW_MASK): Likewise.
+	(PPCPS): Likewise.
+	(powerpc_opcodes): Add all pair singles instructions.
+	* ppc-dis.c (powerpc_dialect): Handle "ppcps".
+	(print_ppc_disassembler_options): Document -Mppcps.
+
 2007-08-21  Andreas Krebbel  <krebbel1@de.ibm.com>
 
 	* s390-mkopc.c (struct s390_cond_ext_format): New global struct.

opcodes/ppc-dis.c

@@ -46,6 +46,9 @@ powerpc_dialect (struct disassemble_info *info)
     dialect |= PPC_OPCODE_64;
 
   if (info->disassembler_options
+      && strstr (info->disassembler_options, "ppcps") != NULL)
+    dialect |= PPC_OPCODE_PPCPS;
+  else if (info->disassembler_options
       && strstr (info->disassembler_options, "booke") != NULL)
     dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
   else if ((info->mach == bfd_mach_ppc_e500)
@@ -365,6 +368,7 @@ the -M switch:\n");
   fprintf (stream, "  e500|e500x2              Disassemble the e500 instructions\n");
   fprintf (stream, "  440                      Disassemble the 440 instructions\n");
   fprintf (stream, "  efs                      Disassemble the EFS instructions\n");
+  fprintf (stream, "  ppcps                    Disassemble the PowerPC paired singles instructions\n");
   fprintf (stream, "  power4                   Disassemble the Power4 instructions\n");
   fprintf (stream, "  power5                   Disassemble the Power5 instructions\n");
   fprintf (stream, "  power6                   Disassemble the Power6 instructions\n");

opcodes/ppc-opc.c

@@ -238,7 +238,9 @@ const struct powerpc_operand powerpc_operands[] =
     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 
   /* The E field in a wrteei instruction.  */
+  /* And the W bit in the pair singles instructions.  */
 #define E DS + 1
+#define PSW E
   { 0x1, 15, NULL, NULL, 0 },
 
   /* The FL1 field in a POWER SC form instruction.  */
@@ -519,12 +521,29 @@ const struct powerpc_operand powerpc_operands[] =
 #define WS EVUIMM_8 + 1
   { 0x7, 11, NULL, NULL, 0 },
 
-  /* The L field in an mtmsrd or A form instruction or W in an X form.  */
+  /* PowerPC paired singles extensions.  */
-#define A_L WS + 1
+  /* W bit in the pair singles instructions for x type instructions.  */
+#define PSWM WS + 1
+  {  0x1, 10, 0, 0, 0 },
+
+  /* IDX bits for quantization in the pair singles instructions.  */
+#define PSQ PSWM + 1
+  {  0x7, 12, 0, 0, 0 },
+
+  /* IDX bits for quantization in the pair singles x-type instructions.  */
+#define PSQM PSQ + 1
+  {  0x7, 7, 0, 0, 0 },
+
+  /* Smaller D field for quantization in the pair singles instructions.  */
+#define PSD PSQM + 1
+  {  0xfff, 0, 0, 0,  PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+
+#define A_L PSD + 1
 #define W A_L
+#define MTMSRD_L W
   { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
 
-#define RMC A_L + 1
+#define RMC MTMSRD_L + 1
   { 0x3, 9, NULL, NULL, 0 },
 
 #define R RMC + 1
@@ -1519,6 +1538,12 @@ extract_tbr (unsigned long insn,
 /* An XO_MASK with the RB field fixed.  */
 #define XORB_MASK (XO_MASK | RB_MASK)
 
+/* An XOPS form instruction for paired singles.  */
+#define XOPS(op, xop, rc) \
+  (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
+#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
+
+
 /* An XS form instruction.  */
 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
 #define XS_MASK XS (0x3f, 0x1ff, 1)
@@ -1551,6 +1576,11 @@ extract_tbr (unsigned long insn,
 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
 #define XUC_MASK      XUC(0x3f, 0x1f)
 
+/* An XW form instruction.  */
+#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
+/* The mask for a G form instruction. rc not supported at present.  */
+#define XW_MASK XW (0x3f, 0x3f, 0)
+
 /* The BO encodings used in extended conditional branch mnemonics.  */
 #define BODNZF	(0x0)
 #define BODNZFP	(0x1)
@@ -1623,6 +1653,7 @@ extract_tbr (unsigned long insn,
 #define PPC750	PPC
 #define PPC7450 PPC
 #define PPC860	PPC
+#define PPCPS	PPC_OPCODE_PPCPS
 #define PPCVEC	PPC_OPCODE_ALTIVEC
 #define	POWER   PPC_OPCODE_POWER
 #define	POWER2	PPC_OPCODE_POWER | PPC_OPCODE_POWER2
@@ -1714,6 +1745,65 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "twi",     OP(3),	OP_MASK,	PPCCOM,		{ TO, RA, SI } },
 { "ti",      OP(3),	OP_MASK,	PWRCOM,		{ TO, RA, SI } },
 
+{ "dcbz_l",    X(4,1014),     XRT_MASK,      PPCPS,  { RA, RB } },
+{ "ps_cmpu0",  X(4 ,0),       X_MASK|(3<<21),PPCPS,  { BF, FRA, FRB } },
+{ "psq_lx",    XW(4,6,0),     XW_MASK,        PPCPS, { FRT, RA, RB, PSWM, PSQM } },
+{ "psq_stx",   XW(4,7,0),     XW_MASK,        PPCPS, { FRS, RA, RB, PSWM, PSQM } },
+{ "ps_sum0",   A(4 ,10,0),    A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_sum0.",  A(4 ,10,1),    A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_sum1",   A(4 ,11,0),    A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_sum1.",  A(4 ,11,1),    A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_muls0",  A(4 ,12,0),    AFRB_MASK,     PPCPS,  { FRT, FRA, FRC } },
+{ "ps_muls0.", A(4 ,12,1),    AFRB_MASK,     PPCPS,  { FRT, FRA, FRC } },
+{ "ps_muls1",  A(4 ,13,0),    AFRB_MASK,     PPCPS,  { FRT, FRA, FRC } },
+{ "ps_muls1.", A(4 ,13,1),    AFRB_MASK,     PPCPS,  { FRT, FRA, FRC } },
+{ "ps_madds0",  A(4 ,14,0),   A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_madds0.", A(4 ,14,1),   A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_madds1",  A(4 ,15,0),   A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_madds1.", A(4 ,15,1),   A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_div",     A(4,18,0),    AFRC_MASK,     PPCPS,  { FRT, FRA, FRB } },
+{ "ps_div.",    A(4,18,1),    AFRC_MASK,     PPCPS,  { FRT, FRA, FRB } },
+{ "ps_sub",     A(4,20,0),    AFRC_MASK,     PPCPS,  { FRT, FRA, FRB } },
+{ "ps_sub.",    A(4,20,1),    AFRC_MASK,     PPCPS,  { FRT, FRA, FRB } },
+{ "ps_add",     A(4,21,0),    AFRC_MASK,     PPCPS,  { FRT, FRA, FRB } },
+{ "ps_add.",    A(4,21,1),    AFRC_MASK,     PPCPS,  { FRT, FRA, FRB } },
+{ "ps_sel",     A(4,23,0),    A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_sel.",    A(4,23,1),    A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_res",     A(4,24,0),    AFRAFRC_MASK,  PPCPS,  { FRT, FRB } },
+{ "ps_res.",    A(4,24,1),    AFRAFRC_MASK,  PPCPS,  { FRT, FRB } },
+{ "ps_mul",     A(4,25,0),    AFRB_MASK,     PPCPS,  { FRT, FRA, FRC } },
+{ "ps_mul.",    A(4,25,1),    AFRB_MASK,     PPCPS,  { FRT, FRA, FRC } },
+{ "ps_rsqrte",  A(4 ,26,0),   AFRAFRC_MASK,  PPCPS,  { FRT, FRB } },
+{ "ps_rsqrte.", A(4 ,26,1),   AFRAFRC_MASK,  PPCPS,  { FRT, FRB } },
+{ "ps_madd",    A(4,29,0),    A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_madd.",   A(4,29,1),    A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_msub",    A(4,28,0),    A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_msub.",   A(4,28,1),    A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_nmsub",   A(4,30,0),    A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_nmsub.",  A(4,30,1),    A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_nmadd",   A(4,31,0),    A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_nmadd.",  A(4,31,1),    A_MASK,        PPCPS,  { FRT,FRA,FRC,FRB } },
+{ "ps_cmpo0",   X(4 ,32),     X_MASK|(3<<21),PPCPS,  { BF, FRA, FRB } },
+{ "psq_lux",    XW(4,38,0),   XW_MASK,        PPCPS,  { FRT, RA, RB, PSWM, PSQM } },
+{ "psq_stux",   XW(4,39,0),   XW_MASK,        PPCPS,  { FRS, RA, RB, PSWM, PSQM } },
+{ "ps_neg",     XRC(4 ,40,0), XRA_MASK,      PPCPS,  { FRT, FRB } },
+{ "ps_neg.",    XRC(4 ,40,1), XRA_MASK,      PPCPS,  { FRT, FRB } },
+{ "ps_cmpu1",   X(4 ,64),   X_MASK|(3<<21),  PPCPS,  { BF, FRA, FRB } },
+{ "ps_mr",      XRC(4 ,72,0), XRA_MASK,      PPCPS,  { FRT, FRB } },
+{ "ps_mr.",     XRC(4 ,72,1), XRA_MASK,      PPCPS,  { FRT, FRB } },
+{ "ps_cmpo1",   X(4 ,96),   X_MASK|(3<<21),  PPCPS,  { BF, FRA, FRB } },
+{ "ps_nabs",    XRC(4 ,136,0), XRA_MASK,     PPCPS,  { FRT, FRB } },
+{ "ps_nabs.",   XRC(4 ,136,1), XRA_MASK,     PPCPS,  { FRT, FRB } },
+{ "ps_abs",     XRC(4,264,0), XRA_MASK,      PPCPS,  { FRT, FRB } },
+{ "ps_abs.",    XRC(4,264,1), XRA_MASK,      PPCPS,  { FRT, FRB } },
+{ "ps_merge00", XOPS(4,528,0), XOPS_MASK,    PPCPS,  { FRT, FRA, FRB } },
+{ "ps_merge00.",XOPS(4,528,1), XOPS_MASK,    PPCPS,  { FRT, FRA, FRB } },
+{ "ps_merge01", XOPS(4,560,0), XOPS_MASK,    PPCPS,  { FRT, FRA, FRB } },
+{ "ps_merge01.",XOPS(4,560,1), XOPS_MASK,    PPCPS,  { FRT, FRA, FRB } },
+{ "ps_merge10", XOPS(4,592,0), XOPS_MASK,    PPCPS,  { FRT, FRA, FRB } },
+{ "ps_merge10.",XOPS(4,592,1), XOPS_MASK,    PPCPS,  { FRT, FRA, FRB } },
+{ "ps_merge11", XOPS(4,624,0), XOPS_MASK,    PPCPS,  { FRT, FRA, FRB } },
+{ "ps_merge11.",XOPS(4,624,1), XOPS_MASK,    PPCPS,  { FRT, FRA, FRB } },
 { "macchw",	XO(4,172,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
 { "macchw.",	XO(4,172,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
 { "macchwo",	XO(4,172,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
@@ -4337,8 +4427,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "lfq",     OP(56),	OP_MASK,	POWER2,		{ FRT, D, RA0 } },
 
+{ "psq_l",   OP(56),    OP_MASK,        PPCPS,          { FRT, PSD, RA, PSW, PSQ } },
+
 { "lfqu",    OP(57),	OP_MASK,	POWER2,		{ FRT, D, RA0 } },
 
+{ "psq_lu",   OP(57),    OP_MASK,       PPCPS,          { FRT, PSD, RA, PSW, PSQ } },
+
 { "lfdp",    OP(57),	OP_MASK,	POWER6,		{ FRT, D, RA0 } },
 
 { "lbze",    DEO(58,0), DE_MASK,	BOOKE64,	{ RT, DE, RA0 } },
@@ -4401,6 +4495,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "fnmadds", A(59,31,0), A_MASK,	PPC,		{ FRT,FRA,FRC,FRB } },
 { "fnmadds.",A(59,31,1), A_MASK,	PPC,		{ FRT,FRA,FRC,FRB } },
 
+{ "psq_st",  OP(60),    OP_MASK,        PPCPS,          { FRS, PSD, RA, PSW, PSQ } },
+{ "psq_stu", OP(61),    OP_MASK,        PPCPS,          { FRS, PSD, RA, PSW, PSQ } },
+
 { "dmul",    XRC(59,34,0), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
 { "dmul.",   XRC(59,34,1), X_MASK,	POWER6,		{ FRT, FRA, FRB } },