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* config/tc-i386.c: Add INFER_ADDR_PREFIX code. Fix 16 bit mode nop.

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This commit is contained in:
Alan Modra
1999-08-03 05:47:26 +00:00
parent a0b3c4fd32
commit c3332e24e8
2 changed files with 440 additions and 399 deletions
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9
gas/ChangeLog
View File

@ -1,3 +1,12 @@
1999-08-03 Etienne Lorrain <etienne.lorrain@ibm.net>
* config/tc-i386.c (f16_3): New. Fixes 16 bit 3 byte nop.
1999-08-03 Alan Modra <alan@spri.levels.unisa.edu.au>
* config/tc-i386.c (i386_operand): Add INFER_ADDR_PREFIX code, but
don't enable it by default. White space changes.
1999-07-30 Jakub Jelinek <jj@ultra.linux.cz> 1999-07-30 Jakub Jelinek <jj@ultra.linux.cz>
* config/tc-sparc.c (md_longopts): Add --no-undeclared-regs option. * config/tc-sparc.c (md_longopts): Add --no-undeclared-regs option.

34
gas/config/tc-i386.c
View File

@ -40,6 +40,10 @@
#define REGISTER_WARNINGS 1 #define REGISTER_WARNINGS 1
#endif #endif
#ifndef INFER_ADDR_PREFIX
#define INFER_ADDR_PREFIX 0
#endif
#ifndef SCALE1_WHEN_NO_INDEX #ifndef SCALE1_WHEN_NO_INDEX
/* Specifying a scale factor besides 1 when there is no index is /* Specifying a scale factor besides 1 when there is no index is
futile. eg. `mov (%ebx,2),%al' does exactly the same as futile. eg. `mov (%ebx,2),%al' does exactly the same as
@ -343,6 +347,8 @@ i386_align_code (fragP, count)
static const char f32_15[] = static const char f32_15[] =
{0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
static const char f16_3[] =
{0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
static const char f16_4[] = static const char f16_4[] =
{0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
static const char f16_5[] = static const char f16_5[] =
@ -362,7 +368,7 @@ i386_align_code (fragP, count)
f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
}; };
static const char *const f16_patt[] = { static const char *const f16_patt[] = {
f32_1, f32_2, f32_3, f16_4, f16_5, f16_6, f16_7, f16_8, f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
}; };
@ -3650,6 +3656,9 @@ i386_operand (operand_string)
/* Make sure the memory operand we've been dealt is valid. */ /* Make sure the memory operand we've been dealt is valid. */
if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0))
{ {
#if INFER_ADDR_PREFIX
try16:
#endif
if ((i.base_reg if ((i.base_reg
&& ((i.base_reg->reg_type & (Reg16|BaseIndex)) && ((i.base_reg->reg_type & (Reg16|BaseIndex))
!= (Reg16|BaseIndex))) != (Reg16|BaseIndex)))
@ -3661,24 +3670,47 @@ i386_operand (operand_string)
&& i.index_reg->reg_num >= 6 && i.index_reg->reg_num >= 6
&& i.log2_scale_factor == 0)))) && i.log2_scale_factor == 0))))
{ {
#if INFER_ADDR_PREFIX
if (i.prefix[ADDR_PREFIX] == 0)
{
i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
goto try32;
}
else
#endif
{
as_bad (_("`%s' is not a valid %s bit base/index expression"), as_bad (_("`%s' is not a valid %s bit base/index expression"),
operand_string, "16"); operand_string, "16");
return 0; return 0;
} }
} }
}
else else
{ {
#if INFER_ADDR_PREFIX
try32:
#endif
if ((i.base_reg if ((i.base_reg
&& (i.base_reg->reg_type & Reg32) == 0) && (i.base_reg->reg_type & Reg32) == 0)
|| (i.index_reg || (i.index_reg
&& ((i.index_reg->reg_type & (Reg32|BaseIndex)) && ((i.index_reg->reg_type & (Reg32|BaseIndex))
!= (Reg32|BaseIndex)))) != (Reg32|BaseIndex))))
{ {
#if INFER_ADDR_PREFIX
if (i.prefix[ADDR_PREFIX] == 0)
{
i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
goto try16;
}
else
#endif
{
as_bad (_("`%s' is not a valid %s bit base/index expression"), as_bad (_("`%s' is not a valid %s bit base/index expression"),
operand_string, "32"); operand_string, "32");
return 0; return 0;
} }
} }
}
i.mem_operands++; i.mem_operands++;
} }
else else