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bpf: opcodes, gas: support for signed load V4 instructions

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This commit adds the signed load to register (ldxs*) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.

Tested in bpf-unknown-none.

include/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/bpf.h (enum bpf_insn_id): Add entries for signed load
	instructions.
	(BPF_MODE_SMEM): Define.

opcodes/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
	instructions.

gas/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/mem.s: Add signed load instructions.
	* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
	* testsuite/gas/bpf/mem.d: Likewise.
	* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
	* testsuite/gas/bpf/mem-be.d: Likewise.
	* doc/c-bpf.texi (BPF Instructions): Document the signed load
	instructions.
This commit is contained in:
Jose E. Marchesi
2023-07-21 19:47:49 +02:00
parent 2f3dbc5fb5
commit c24fd9547f
12 changed files with 78 additions and 0 deletions
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6
include/ChangeLog
View File

@ -1,3 +1,9 @@
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (enum bpf_insn_id): Add entries for signed load
instructions.
(BPF_MODE_SMEM): Define.
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (BPF_OFFSET16_MOVS8): Define.

3
include/opcode/bpf.h
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@ -112,6 +112,7 @@ typedef uint64_t bpf_insn_word;
#define BPF_MODE_IND ((uint64_t)0x40 << 56)
#define BPF_MODE_MEM ((uint64_t)0x60 << 56)
#define BPF_MODE_ATOMIC ((uint64_t)0xc0 << 56)
#define BPF_MODE_SMEM ((uint64_t)0x80 << 56)
#define BPF_SIZE_W ((uint64_t)0x00 << 56)
#define BPF_SIZE_H ((uint64_t)0x08 << 56)
@ -186,6 +187,8 @@ enum bpf_insn_id
BPF_INSN_LDINDB, BPF_INSN_LDINDH, BPF_INSN_LDINDW, BPF_INSN_LDINDDW,
/* Generic load instructions (to register.) */
BPF_INSN_LDXB, BPF_INSN_LDXH, BPF_INSN_LDXW, BPF_INSN_LDXDW,
/* Generic signed load instructions. */
BPF_INSN_LDXSB, BPF_INSN_LDXSH, BPF_INSN_LDXSW, BPF_INSN_LDXSDW,
/* Generic store instructions (from register.) */
BPF_INSN_STXBR, BPF_INSN_STXHR, BPF_INSN_STXWR, BPF_INSN_STXDWR,
BPF_INSN_STXBI, BPF_INSN_STXHI, BPF_INSN_STXWI, BPF_INSN_STXDWI,