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ld: aarch64: fix TLS relaxation where TCB_SIZE is used
TCB_SIZE is 2*sizeof(void *), which is 0x10 for lp64, and 0x8 for ilp32. During relaxation, ld goes to do a replace: bl __tls_get_addr => add R0, R0, TCB_SIZE But actual implementation is: bfd_putl32 (0x91004000, contents + rel->r_offset + 4); Which is equivalent of add x0, x0, 0x10. This is wrong for ilp32. The possible fix for it is: bfd_putl32 (0x91000000 | (TCB_SIZE<<10), contents + rel->r_offset + 4); But ilp32 also needs w-registers, so it's simpler to put proper instruction in #if/#else condition. There are 2 such relaxations in elfNN_aarch64_tls_relax(), and so 2 new tests added for ilp32 mode to test it. Yury * bfd/elfnn-aarch64.c: fix TLS relaxations for ilp32 where TCB_SIZE is used. * ld/testsuite/ld-aarch64/aarch64-elf.exp: Add tests for the case. * ld/testsuite/ld-aarch64/tls-relax-ld-le-small-ilp32.d: New file. * ld/testsuite/ld-aarch64/tls-relax-ld-le-tiny-ilp32.d: New file. Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>
This commit is contained in:
@ -1,3 +1,8 @@
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2016-12-14 Yury Norov <ynorov@caviumnetworks.com>
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* bfd/elfnn-aarch64.c: fix TLS relaxations for ilp32 where
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TCB_SIZE is used.
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2016-12-13 Alan Modra <amodra@gmail.com>
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2016-12-13 Alan Modra <amodra@gmail.com>
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* elf64-hppa.c (elf64_hppa_modify_segment_map): Don't add PHDR
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* elf64-hppa.c (elf64_hppa_modify_segment_map): Don't add PHDR
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@ -5951,8 +5951,9 @@ elfNN_aarch64_tls_relax (struct elf_aarch64_link_hash_table *globals,
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case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
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case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
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/* LD->LE relaxation (tiny):
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/* LD->LE relaxation (tiny):
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adr x0, :tlsldm:x => mrs x0, tpidr_el0
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adr x0, :tlsldm:x => mrs x0, tpidr_el0
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bl __tls_get_addr => add x0, x0, TCB_SIZE
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bl __tls_get_addr => add R0, R0, TCB_SIZE
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*/
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Where R is x for lp64 mode, and w for ilp32 mode. */
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if (is_local)
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if (is_local)
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{
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{
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BFD_ASSERT (rel->r_offset + 4 == rel[1].r_offset);
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BFD_ASSERT (rel->r_offset + 4 == rel[1].r_offset);
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@ -5960,7 +5961,11 @@ elfNN_aarch64_tls_relax (struct elf_aarch64_link_hash_table *globals,
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/* No need of CALL26 relocation for tls_get_addr. */
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/* No need of CALL26 relocation for tls_get_addr. */
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rel[1].r_info = ELFNN_R_INFO (STN_UNDEF, R_AARCH64_NONE);
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rel[1].r_info = ELFNN_R_INFO (STN_UNDEF, R_AARCH64_NONE);
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bfd_putl32 (0xd53bd040, contents + rel->r_offset + 0);
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bfd_putl32 (0xd53bd040, contents + rel->r_offset + 0);
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#if ARCH_SIZE == 64
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bfd_putl32 (0x91004000, contents + rel->r_offset + 4);
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bfd_putl32 (0x91004000, contents + rel->r_offset + 4);
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#else
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bfd_putl32 (0x11002000, contents + rel->r_offset + 4);
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#endif
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return bfd_reloc_ok;
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return bfd_reloc_ok;
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}
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}
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return bfd_reloc_continue;
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return bfd_reloc_continue;
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@ -5978,17 +5983,22 @@ elfNN_aarch64_tls_relax (struct elf_aarch64_link_hash_table *globals,
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case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
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case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
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/* LD->LE relaxation (small):
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/* LD->LE relaxation (small):
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add x0, #:tlsldm_lo12:x => add x0, x0, TCB_SIZE
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add x0, #:tlsldm_lo12:x => add R0, R0, TCB_SIZE
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bl __tls_get_addr => nop
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bl __tls_get_addr => nop
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*/
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Where R is x for lp64 mode, and w for ilp32 mode. */
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if (is_local)
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if (is_local)
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{
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{
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BFD_ASSERT (rel->r_offset + 4 == rel[1].r_offset);
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BFD_ASSERT (rel->r_offset + 4 == rel[1].r_offset);
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BFD_ASSERT (ELFNN_R_TYPE (rel[1].r_info) == AARCH64_R (CALL26));
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BFD_ASSERT (ELFNN_R_TYPE (rel[1].r_info) == AARCH64_R (CALL26));
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/* No need of CALL26 relocation for tls_get_addr. */
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/* No need of CALL26 relocation for tls_get_addr. */
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rel[1].r_info = ELFNN_R_INFO (STN_UNDEF, R_AARCH64_NONE);
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rel[1].r_info = ELFNN_R_INFO (STN_UNDEF, R_AARCH64_NONE);
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#if ARCH_SIZE == 64
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bfd_putl32 (0x91004000, contents + rel->r_offset + 0);
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bfd_putl32 (0x91004000, contents + rel->r_offset + 0);
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bfd_putl32 (0xd503201f, contents + rel->r_offset + 4);
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#else
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bfd_putl32 (0x11002000, contents + rel->r_offset + 0);
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#endif
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bfd_putl32 (INSN_NOP, contents + rel->r_offset + 4);
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return bfd_reloc_ok;
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return bfd_reloc_ok;
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}
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}
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return bfd_reloc_continue;
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return bfd_reloc_continue;
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@ -1,3 +1,10 @@
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2016-12-14 Yury Norov <ynorov@caviumnetworks.com>
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* ld/testsuite/ld-aarch64/aarch64-elf.exp: Add tests for tiny and
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small ld-le relaxations in ilp32 mode.
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* ld/testsuite/ld-aarch64/tls-relax-ld-le-small-ilp32.d: New file.
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* ld/testsuite/ld-aarch64/tls-relax-ld-le-tiny-ilp32.d: New file.
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2016-12-13 Jiong Wang <jiong.wang@arm.com>
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2016-12-13 Jiong Wang <jiong.wang@arm.com>
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* testsuite/ld-aarch64/aarch64-elf.exp (aarch64_choose_lp64_emul): New
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* testsuite/ld-aarch64/aarch64-elf.exp (aarch64_choose_lp64_emul): New
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@ -228,7 +228,9 @@ run_dump_test_lp64 "tls-relax-large-desc-le-be"
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run_dump_test "tls-relax-gdesc-ie"
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run_dump_test "tls-relax-gdesc-ie"
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run_dump_test "tls-relax-ie-le"
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run_dump_test "tls-relax-ie-le"
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run_dump_test "tls-relax-ld-le-small"
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run_dump_test "tls-relax-ld-le-small"
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run_dump_test "tls-relax-ld-le-small-ilp32"
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run_dump_test "tls-relax-ld-le-tiny"
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run_dump_test "tls-relax-ld-le-tiny"
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run_dump_test "tls-relax-ld-le-tiny-ilp32"
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run_dump_test "tls-desc-ie"
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run_dump_test "tls-desc-ie"
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run_dump_test "tls-relax-gdesc-ie-2"
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run_dump_test "tls-relax-gdesc-ie-2"
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run_dump_test "tls-relax-gdesc-le-2"
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run_dump_test "tls-relax-gdesc-le-2"
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14
ld/testsuite/ld-aarch64/tls-relax-ld-le-small-ilp32.d
Normal file
14
ld/testsuite/ld-aarch64/tls-relax-ld-le-small-ilp32.d
Normal file
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#source: tls-relax-ld-le-small.s
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#as: -mabi=ilp32
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#ld: -m [aarch64_choose_ilp32_emul] -T relocs-ilp32.ld -e0
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#objdump: -dr
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#...
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+10000: 910003fd mov x29, sp
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+10004: d53bd040 mrs x0, tpidr_el0
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+10008: 11002000 add w0, w0, #0x8
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+1000c: d503201f nop
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+10010: d503201f nop
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+10014: 91400001 add x1, x0, #0x0, lsl #12
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+10018: 91000021 add x1, x1, #0x0
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+1001c: 90000000 adrp x0, 10000 <.*>
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+10020: d65f03c0 ret
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ld/testsuite/ld-aarch64/tls-relax-ld-le-tiny-ilp32.d
Normal file
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ld/testsuite/ld-aarch64/tls-relax-ld-le-tiny-ilp32.d
Normal file
@ -0,0 +1,13 @@
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#source: tls-relax-ld-le-tiny.s
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#as: -mabi=ilp32
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#ld: -m [aarch64_choose_ilp32_emul] -T relocs-ilp32.ld -e0
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#objdump: -dr
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#...
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+10000: 910003fd mov x29, sp
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+10004: d53bd040 mrs x0, tpidr_el0
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+10008: 11002000 add w0, w0, #0x8
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+1000c: d503201f nop
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+10010: 91400001 add x1, x0, #0x0, lsl #12
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+10014: 91000021 add x1, x1, #0x0
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+10018: 90000000 adrp x0, 10000 <main>
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+1001c: d65f03c0 ret
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