mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-06-20 18:08:24 +08:00
Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.
opcodes * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
(insert_nps_misc_imm_offset): New function.
(extract_nps_misc imm_offset): New function.
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
gas * testsuite/gas/arc/nps400-12.s: New file.
* testsuite/gas/arc/nps400-12.d: New file.
This commit is contained in:
Rinat Zelig
committed by
Nick Clifton
Nick Clifton
parent
cf31b44f3c
commit
c0c31e91ad
@ -1,3 +1,8 @@
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2017-03-27 Rinat Zelig <rinat@mellanox.com>
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* testsuite/gas/arc/nps400-12.s: New file.
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* testsuite/gas/arc/nps400-12.d: New file.
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2017-03-24 Thomas preud'homme <thomas.preudhomme@arm.com>
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2017-03-24 Thomas preud'homme <thomas.preudhomme@arm.com>
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* config/tc-arm.: (md_begin): Set selected_cpu from *mcpu_cpu_opt when
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* config/tc-arm.: (md_begin): Set selected_cpu from *mcpu_cpu_opt when
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59
gas/testsuite/gas/arc/nps400-12.d
Normal file
59
gas/testsuite/gas/arc/nps400-12.d
Normal file
@ -0,0 +1,59 @@
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#as: -mcpu=nps400
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#objdump: -dr
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.*: +file format .*arc.*
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Disassembly of section .text:
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[0-9a-f]+ <.*>:
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0: 3815 0042 whash r2,\[cm:r0\],r1
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4: 3b15 0385 whash r5,\[cm:r3\],r14
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8: 3815 007e whash 0,\[cm:r0\],r1
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c: 3b15 03be whash 0,\[cm:r3\],r14
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10: 3855 01c2 whash r2,\[cm:r0\],0x7
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14: 3855 01fe whash 0,\[cm:r0\],0x7
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18: 3855 0002 whash r2,\[cm:r0\],0x40
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1c: 3855 003e whash 0,\[cm:r0\],0x40
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20: 4822 4000 mcmp r0,\[cm:r0\],\[cm:r1\],r1
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24: 4822 6000 mcmp\.s r0,\[cm:r0\],\[cm:r1\],r1
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28: 4822 4080 mcmp\.m r0,\[cm:r0\],\[cm:r1\],r1
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2c: 4822 6080 mcmp\.s\.m r0,\[cm:r0\],\[cm:r1\],r1
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30: 4822 0000 mcmp r0,\[cm:r0,r0\],\[cm:r1\],r1
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34: 4822 2000 mcmp\.s r0,\[cm:r0,r0\],\[cm:r1\],r1
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38: 4822 0080 mcmp\.m r0,\[cm:r0,r0\],\[cm:r1\],r1
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3c: 4822 2080 mcmp\.s\.m r0,\[cm:r0,r0\],\[cm:r1\],r1
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40: 4822 4100 mcmp r0,\[cm:r0,0x4\],\[cm:r1\],r1
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44: 4822 6100 mcmp\.s r0,\[cm:r0,0x4\],\[cm:r1\],r1
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48: 4822 4180 mcmp\.m r0,\[cm:r0,0x4\],\[cm:r1\],r1
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4c: 4822 6180 mcmp\.s\.m r0,\[cm:r0,0x4\],\[cm:r1\],r1
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50: 4822 4200 mcmp r0,\[cm:r0,0x8\],\[cm:r1\],r1
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54: 4822 4300 mcmp r0,\[cm:r0,0xc\],\[cm:r1\],r1
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58: 4822 c004 mcmp r0,\[cm:r0\],\[cm:r1\],0x4
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5c: 4822 e004 mcmp\.s r0,\[cm:r0\],\[cm:r1\],0x4
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60: 4822 c084 mcmp\.m r0,\[cm:r0\],\[cm:r1\],0x4
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64: 4822 e088 mcmp\.s\.m r0,\[cm:r0\],\[cm:r1\],0x8
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68: 4822 c07f mcmp r0,\[cm:r0\],\[cm:r1\],0x7f
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6c: 4822 c204 mcmp r0,\[cm:r0,0x8\],\[cm:r1\],0x4
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70: 4822 e204 mcmp\.s r0,\[cm:r0,0x8\],\[cm:r1\],0x4
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74: 4822 c284 mcmp\.m r0,\[cm:r0,0x8\],\[cm:r1\],0x4
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78: 4822 e284 mcmp\.s\.m r0,\[cm:r0,0x8\],\[cm:r1\],0x4
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7c: 4822 802e mcmp r0,\[cm:r0,r0\],\[cm:r1\],0x2e
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80: 4822 a046 mcmp\.s r0,\[cm:r0,r0\],\[cm:r1\],0x46
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84: 4822 80c8 mcmp\.m r0,\[cm:r0,r0\],\[cm:r1\],0x48
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88: 4822 a0fd mcmp\.s\.m r0,\[cm:r0,r0\],\[cm:r1\],0x7d
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8c: 3856 003e asri 0,r0
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90: 3856 007e asri\.core 0,r0
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94: 3856 00be asri\.clsr 0,r0
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98: 3856 00fe asri\.all 0,r0
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9c: 3856 013e asri\.gic 0,r0
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a0: 3856 017e rspi\.gic 0,r0
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a4: 385b 003e wkup 0,r0
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a8: 385b 013e wkup\.cl
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ac: 3a2f 0024 getsti r2,\[cm:r0\]
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b0: 3e2f 7024 getsti 0,\[cm:r0\]
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000000b4 <label>:
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b4: 3a2f 0025 getrtc r2,\[cm:r0\]
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b8: 3e2f 7025 getrtc 0,\[cm:r0\]
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bc: 07f8 ffd5 bnj -8
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c0: 07f4 ffd7 bnm -12
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c4: 07f0 ffd8 bnt -16
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71
gas/testsuite/gas/arc/nps400-12.s
Normal file
71
gas/testsuite/gas/arc/nps400-12.s
Normal file
@ -0,0 +1,71 @@
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.text
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; Miscellaneous
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; whash
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whash r2,[cm:r0],r1
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whash r5,[cm:r3],r14
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whash 0,[cm:r0],r1
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whash 0,[cm:r3],r14
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whash r2,[cm:r0],7
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whash 0,[cm:r0],7
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whash r2,[cm:r0],64
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whash 0,[cm:r0],64
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; mcmp
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mcmp r0,[cm:r0],[cm:r1],r1
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mcmp.s r0,[cm:r0],[cm:r1],r1
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mcmp.m r0,[cm:r0],[cm:r1],r1
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mcmp.s.m r0,[cm:r0],[cm:r1],r1
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mcmp r0,[cm:r0,r0],[cm:r1],r1
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mcmp.s r0,[cm:r0,r0],[cm:r1],r1
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mcmp.m r0,[cm:r0,r0],[cm:r1],r1
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mcmp.s.m r0,[cm:r0,r0],[cm:r1],r1
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mcmp r0,[cm:r0,4],[cm:r1],r1
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mcmp.s r0,[cm:r0,4],[cm:r1],r1
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mcmp.m r0,[cm:r0,4],[cm:r1],r1
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mcmp.s.m r0,[cm:r0,4],[cm:r1],r1
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mcmp r0,[cm:r0,8],[cm:r1],r1
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mcmp r0,[cm:r0,12],[cm:r1],r1
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mcmp r0,[cm:r0],[cm:r1],4
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mcmp.s r0,[cm:r0],[cm:r1],4
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mcmp.m r0,[cm:r0],[cm:r1],4
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mcmp.s.m r0,[cm:r0],[cm:r1],8
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mcmp r0,[cm:r0],[cm:r1],127
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mcmp r0,[cm:r0,8],[cm:r1],4
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mcmp.s r0,[cm:r0,8],[cm:r1],4
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mcmp.m r0,[cm:r0,8],[cm:r1],4
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mcmp.s.m r0,[cm:r0,8],[cm:r1],4
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mcmp r0,[cm:r0,r0],[cm:r1],46
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mcmp.s r0,[cm:r0,r0],[cm:r1],70
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mcmp.m r0,[cm:r0,r0],[cm:r1],72
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mcmp.s.m r0,[cm:r0,r0],[cm:r1],125
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;asri
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asri 0, r0
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asri.core 0, r0
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asri.clsr 0,r0
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asri.all 0,r0
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asri.gic 0,r0
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rspi.gic 0,r0
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;wkup
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wkup 0,r0
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wkup.cl
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;getsti
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getsti r2,[cm:r0]
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getsti 0,[cm:r0]
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label:
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;getrtc
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getrtc r2,[cm:r0]
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getrtc 0,[cm:r0]
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;b<cc>
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bnj label
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bnm label
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bnt label
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@ -1,3 +1,7 @@
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2017-03-27 Rinat Zelig <rinat@mellanox.com>
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* opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
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2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* opcode/s390.h (S390_INSTR_FLAG_VX2): Remove.
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* opcode/s390.h (S390_INSTR_FLAG_VX2): Remove.
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@ -68,6 +68,7 @@ typedef enum
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LOGICAL,
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LOGICAL,
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LOOP,
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LOOP,
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MEMORY,
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MEMORY,
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MISC,
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MOVE,
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MOVE,
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MPY,
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MPY,
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NET,
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NET,
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@ -77,6 +78,7 @@ typedef enum
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PUSH,
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PUSH,
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STORE,
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STORE,
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SUB,
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SUB,
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ULTRAIP,
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XY
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XY
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} insn_class_t;
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} insn_class_t;
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@ -1,3 +1,13 @@
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2017-03-27 Rinat Zelig <rinat@mellanox.com>
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* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
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* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
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F_NPS_M, F_NPS_CORE, F_NPS_ALL.
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(insert_nps_misc_imm_offset): New function.
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(extract_nps_misc imm_offset): New function.
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(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
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(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
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2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* s390-mkopc.c (main): Remove vx2 check.
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* s390-mkopc.c (main): Remove vx2 check.
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@ -905,6 +905,78 @@ XLDST_LIKE("xst", 0xe)
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/* cp32<.na> [xd:src1,src2,src2,src2], [cm:src2] */
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/* cp32<.na> [xd:src1,src2,src2,src2], [cm:src2] */
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{ "cp32", 0x48078181, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
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{ "cp32", 0x48078181, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
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/* Ultra IP Instructions. */
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/* uip<.na> dst, [cm:src2], [cm:src1] */
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{ "uip", 0x480740a2, 0xf81fc1e3, ARC_OPCODE_ARC700, ULTRAIP, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B, BRAKETdup }, { C_NPS_NA }},
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/* uip<.na> dst, [cm:src2], [cm:src1], src2 */
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{ "uip", 0x480700a2, 0xf81fc1e3, ARC_OPCODE_ARC700, ULTRAIP, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B, BRAKETdup, NPS_R_SRC2_3B }, { C_NPS_NA }},
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/* Miscellaneous Instructions. */
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/* whash dst,[cm:src1],src2 */
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{ "whash", 0x38150000, 0xf8ff0000, ARC_OPCODE_ARC700, MISC, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RC }, { 0 }},
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/* whash 0,[cm:src1],src2 */
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{ "whash", 0x3815003e, 0xf8ff003f, ARC_OPCODE_ARC700, MISC, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RC }, { 0 }},
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/* whash dst,[cm:src1],size */
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{ "whash", 0x38550000, 0xf8ff0000, ARC_OPCODE_ARC700, MISC, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, NPS_WHASH_SIZE }, { 0 }},
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/* whash 0,[cm:src1],size */
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{ "whash", 0x3855003e, 0xf8ff003f, ARC_OPCODE_ARC700, MISC, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, NPS_WHASH_SIZE }, { 0 }},
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/* mcmp<.s><.m> dst,[cm:src1],[cm:src2],src2 */
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{ "mcmp", 0x48024000, 0xf81fdf7f, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, NPS_R_SRC2_3B }, { C_NPS_SR, C_NPS_M }},
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/* mcmp<.s><.m> dst,[cm:src1,src1],[cm:src2],src2 */
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{ "mcmp", 0x48020000, 0xf81fdf7f, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B, NPS_DPI_SRC1_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, NPS_R_SRC2_3B }, { C_NPS_SR, C_NPS_M }},
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/* mcmp.<s><.m> dst,[cm:src1,offset],[cm:src2],src2 */
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{ "mcmp", 0x48024000, 0xf81fc000, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B,
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NPS_MISC_IMM_OFFSET, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, NPS_R_SRC2_3B }, { C_NPS_SR, C_NPS_M }},
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/* mcmp<.s><.m> dst,[cm:src1],[cm: src2],size */
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{ "mcmp", 0x4802c000, 0xf81fcf00, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, NPS_MISC_IMM_SIZE }, { C_NPS_SR, C_NPS_M }},
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/* mcmp<.s><.m> dst,[cm:src1,offset],[cm:src2],size */
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{ "mcmp", 0x4802c000, 0xf81fc000, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B,
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NPS_MISC_IMM_OFFSET, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, NPS_MISC_IMM_SIZE }, { C_NPS_SR, C_NPS_M }},
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/* mcmp<.s><.m> dst,[cm:src1,src1],[cm:src2],size */
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{ "mcmp", 0x48028000, 0xf81fdf00, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B, NPS_DPI_SRC1_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, NPS_MISC_IMM_SIZE }, { C_NPS_SR, C_NPS_M }},
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#define ASRI_LIKE(SUBOP2, FLAG) \
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{ "asri", (0x3856003e | (SUBOP2 << 6)), 0xf8ff8fff, ARC_OPCODE_ARC700, MISC, NPS400, { ZA, RB }, { FLAG }},
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ASRI_LIKE (0x0, 0)
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||||||
|
ASRI_LIKE (0x1, C_NPS_CORE)
|
||||||
|
ASRI_LIKE (0x2, C_NPS_CLSR)
|
||||||
|
ASRI_LIKE (0x3, C_NPS_ALL)
|
||||||
|
ASRI_LIKE (0x4, C_NPS_GIC)
|
||||||
|
|
||||||
|
/* rspi.gic 0,src1 */
|
||||||
|
{ "rspi", 0x3856017e, 0xf8ff8fff, ARC_OPCODE_ARC700, MISC, NPS400, { ZA, RB }, { C_NPS_RSPI_GIC }},
|
||||||
|
|
||||||
|
/* wkup.cl */
|
||||||
|
{ "wkup", 0x385b013e, 0xf8ff8fff, ARC_OPCODE_ARC700, MISC, NPS400, { 0 }, { C_NPS_CL }},
|
||||||
|
|
||||||
|
/* wkup 0, src2 */
|
||||||
|
{ "wkup", 0x385b003e, 0xf8ff8fff, ARC_OPCODE_ARC700, MISC, NPS400, { ZA, RC }, { 0 }},
|
||||||
|
|
||||||
|
/* getsti dst,[cm:src2] */
|
||||||
|
{ "getsti", 0x382f0024, 0xf8ff803f, ARC_OPCODE_ARC700, MISC, NPS400, { RB, BRAKET, NPS_CM, COLON, RC, BRAKETdup }, { 0 }},
|
||||||
|
|
||||||
|
/* getsti 0, [cm:src2] */
|
||||||
|
{ "getsti", 0x3e2f7024, 0xfffff03f, ARC_OPCODE_ARC700, MISC, NPS400, { ZA, BRAKET, NPS_CM, COLON, RC, BRAKETdup }, { 0 }},
|
||||||
|
|
||||||
|
/* getrtc dst,[cm:src2] */
|
||||||
|
{ "getrtc", 0x382f0025, 0xf8ff803f, ARC_OPCODE_ARC700, MISC, NPS400, { RB, BRAKET, NPS_CM, COLON, RC, BRAKETdup }, { 0 }},
|
||||||
|
|
||||||
|
/* getrtc 0, [cm:src2] */
|
||||||
|
{ "getrtc", 0x3e2f7025, 0xfffff03f, ARC_OPCODE_ARC700, MISC, NPS400, { ZA, BRAKET, NPS_CM, COLON, RC, BRAKETdup }, { 0 }},
|
||||||
|
|
||||||
/* Atomic Operations. */
|
/* Atomic Operations. */
|
||||||
|
|
||||||
/* exc<.di><.f> a,a,[xa:b] */
|
/* exc<.di><.f> a,a,[xa:b] */
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user