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RISC-V: Add support for the Zvbc extension

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Zvbc is part of the crypto vector extensions.

This extension adds the following instructions:
- vclmul.[vv,vx]
- vclmulh.[vv,vx]

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvbc.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvbc.d: New test.
	* testsuite/gas/riscv/zvbc.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VCLMUL_VV): New.
	(MASK_VCLMUL_VV): New.
	(MATCH_VCLMUL_VX): New.
	(MASK_VCLMUL_VX): New.
	(MATCH_VCLMULH_VV): New.
	(MASK_VCLMULH_VV): New.
	(MATCH_VCLMULH_VX): New.
	(MASK_VCLMULH_VX): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction class
	  support for Zvbc.

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvbc instruction.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:
Nathan Huckleberry
2023-06-30 22:43:40 +02:00
committed by Jeff Law
parent c8cb37347f
commit c0a98a853d
6 changed files with 50 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
include/opcode/riscv-opc.h
View File

@ -2154,6 +2154,15 @@
#define MASK_VWSLL_VV 0xfc00707f
#define MATCH_VWSLL_VX 0xd4004057
#define MASK_VWSLL_VX 0xfc00707f
/* Zvbc instructions. */
#define MATCH_VCLMUL_VV 0x30002057
#define MASK_VCLMUL_VV 0xfc00707f
#define MATCH_VCLMUL_VX 0x30006057
#define MASK_VCLMUL_VX 0xfc00707f
#define MATCH_VCLMULH_VV 0x34002057
#define MASK_VCLMULH_VV 0xfc00707f
#define MATCH_VCLMULH_VX 0x34006057
#define MASK_VCLMULH_VX 0xfc00707f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@ -3280,6 +3289,11 @@ DECLARE_INSN(vror_vx, MATCH_VROR_VX, MASK_VROR_VX)
DECLARE_INSN(vwsll_vi, MATCH_VWSLL_VI, MASK_VWSLL_VI)
DECLARE_INSN(vwsll_vv, MATCH_VWSLL_VV, MASK_VWSLL_VV)
DECLARE_INSN(vwsll_vx, MATCH_VWSLL_VX, MASK_VWSLL_VX)
/* Zvbc instructions. */
DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV)
DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX)
DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV)
DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */

1
include/opcode/riscv.h
View File

@ -415,6 +415,7 @@ enum riscv_insn_class
INSN_CLASS_V,
INSN_CLASS_ZVEF,
INSN_CLASS_ZVBB,
INSN_CLASS_ZVBC,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,