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Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500
PPC_OPCODE_* renumbered to fill the gaps left by previous patches, and reordered chronologically just because. I kept PPC_OPCODE_TMR because presumably it might be used in future APUinfo for e6500. include/ * opcode/ppc.h (PPC_OPCODE_*): Renumber and order chronologically. (PPC_OPCODE_SPE): Comment on this and other bits used for APUinfo. opcodes/ * ppc-dis.c (ppc_opts): Formatting. Set PPC_OPCODE_TMR for e6500. * ppc-opc.c (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
This commit is contained in:
Alan Modra
@ -82,24 +82,24 @@ extern const int vle_num_opcodes;
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/* Opcode is defined for the POWER2 (Rios 2) architecture. */
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#define PPC_OPCODE_POWER2 0x4ull
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/* Opcode is only defined on 64 bit architectures. */
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#define PPC_OPCODE_64 0x8ull
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/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
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is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
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but it also supports many additional POWER instructions. */
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#define PPC_OPCODE_601 0x8ull
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#define PPC_OPCODE_601 0x10ull
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/* Opcode is supported in both the Power and PowerPC architectures
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(ie, compiler's -mcpu=common or assembler's -mcom). More than just
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the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
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and PPC_OPCODE_POWER2 because many instructions changed mnemonics
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between POWER and POWERPC. */
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#define PPC_OPCODE_COMMON 0x10ull
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#define PPC_OPCODE_COMMON 0x20ull
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/* Opcode is supported for any Power or PowerPC platform (this is
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for the assembler's -many option, and it eliminates duplicates). */
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#define PPC_OPCODE_ANY 0x20ull
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/* Opcode is only defined on 64 bit architectures. */
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#define PPC_OPCODE_64 0x40ull
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#define PPC_OPCODE_ANY 0x40ull
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/* Opcode is supported as part of the 64-bit bridge. */
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#define PPC_OPCODE_64_BRIDGE 0x80ull
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@ -113,104 +113,107 @@ extern const int vle_num_opcodes;
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/* Opcode is supported by PowerPC BookE processor. */
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#define PPC_OPCODE_BOOKE 0x400ull
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/* Opcode is supported by PowerPC 440 processor. */
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#define PPC_OPCODE_440 0x800ull
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/* Opcode is only supported by Power4 architecture. */
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#define PPC_OPCODE_POWER4 0x1000ull
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#define PPC_OPCODE_POWER4 0x800ull
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/* Opcode is only supported by Power7 architecture. */
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#define PPC_OPCODE_POWER7 0x2000ull
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/* Opcode is only supported by e500x2 Core.
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This bit, PPC_OPCODE_EFS, PPC_OPCODE_VLE, and all those with APU in
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their comment mark opcodes so that when those instructions are used
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an APUinfo entry can be generated. */
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#define PPC_OPCODE_SPE 0x1000ull
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/* Opcode is only supported by e500x2 Core. */
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#define PPC_OPCODE_SPE 0x4000ull
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/* Opcode is supported by e500x2 Integer select APU. */
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#define PPC_OPCODE_ISEL 0x8000ull
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/* Opcode is supported by Integer select APU. */
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#define PPC_OPCODE_ISEL 0x2000ull
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/* Opcode is an e500 SPE floating point instruction. */
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#define PPC_OPCODE_EFS 0x10000ull
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#define PPC_OPCODE_EFS 0x4000ull
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/* Opcode is supported by branch locking APU. */
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#define PPC_OPCODE_BRLOCK 0x20000ull
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#define PPC_OPCODE_BRLOCK 0x8000ull
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/* Opcode is supported by performance monitor APU. */
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#define PPC_OPCODE_PMR 0x40000ull
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#define PPC_OPCODE_PMR 0x10000ull
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/* Opcode is supported by cache locking APU. */
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#define PPC_OPCODE_CACHELCK 0x80000ull
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#define PPC_OPCODE_CACHELCK 0x20000ull
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/* Opcode is supported by machine check APU. */
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#define PPC_OPCODE_RFMCI 0x100000ull
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#define PPC_OPCODE_RFMCI 0x40000ull
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/* Opcode is supported by PowerPC 440 processor. */
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#define PPC_OPCODE_440 0x80000ull
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/* Opcode is only supported by Power5 architecture. */
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#define PPC_OPCODE_POWER5 0x200000ull
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#define PPC_OPCODE_POWER5 0x100000ull
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/* Opcode is supported by PowerPC e300 family. */
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#define PPC_OPCODE_E300 0x400000ull
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#define PPC_OPCODE_E300 0x200000ull
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/* Opcode is only supported by Power6 architecture. */
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#define PPC_OPCODE_POWER6 0x800000ull
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#define PPC_OPCODE_POWER6 0x400000ull
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/* Opcode is only supported by PowerPC Cell family. */
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#define PPC_OPCODE_CELL 0x1000000ull
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#define PPC_OPCODE_CELL 0x800000ull
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/* Opcode is supported by CPUs with paired singles support. */
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#define PPC_OPCODE_PPCPS 0x2000000ull
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#define PPC_OPCODE_PPCPS 0x1000000ull
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/* Opcode is supported by Power E500MC */
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#define PPC_OPCODE_E500MC 0x4000000ull
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#define PPC_OPCODE_E500MC 0x2000000ull
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/* Opcode is supported by PowerPC 405 processor. */
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#define PPC_OPCODE_405 0x8000000ull
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#define PPC_OPCODE_405 0x4000000ull
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/* Opcode is supported by Vector-Scalar (VSX) Unit */
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#define PPC_OPCODE_VSX 0x10000000ull
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#define PPC_OPCODE_VSX 0x8000000ull
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/* Opcode is only supported by Power7 architecture. */
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#define PPC_OPCODE_POWER7 0x10000000ull
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/* Opcode is supported by A2. */
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#define PPC_OPCODE_A2 0x20000000ull
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#define PPC_OPCODE_A2 0x20000000ull
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/* Opcode is supported by PowerPC 476 processor. */
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#define PPC_OPCODE_476 0x40000000ull
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/* Opcode is supported by AppliedMicro Titan core */
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#define PPC_OPCODE_TITAN 0x80000000ull
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#define PPC_OPCODE_TITAN 0x80000000ull
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/* Opcode which is supported by the e500 family */
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#define PPC_OPCODE_E500 0x100000000ull
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#define PPC_OPCODE_E500 0x100000000ull
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/* Opcode is supported by Power E6500 */
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#define PPC_OPCODE_E6500 0x400000000ull
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#define PPC_OPCODE_E6500 0x200000000ull
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/* Opcode is supported by Thread management APU */
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#define PPC_OPCODE_TMR 0x800000000ull
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#define PPC_OPCODE_TMR 0x400000000ull
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/* Opcode which is supported by the VLE extension. */
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#define PPC_OPCODE_VLE 0x1000000000ull
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#define PPC_OPCODE_VLE 0x800000000ull
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/* Opcode is only supported by Power8 architecture. */
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#define PPC_OPCODE_POWER8 0x2000000000ull
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#define PPC_OPCODE_POWER8 0x1000000000ull
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/* Opcode is supported by ppc750cl. */
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#define PPC_OPCODE_750 0x4000000000ull
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#define PPC_OPCODE_750 0x2000000000ull
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/* Opcode is supported by ppc7450. */
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#define PPC_OPCODE_7450 0x8000000000ull
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#define PPC_OPCODE_7450 0x4000000000ull
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/* Opcode is supported by ppc821/850/860. */
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#define PPC_OPCODE_860 0x10000000000ull
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#define PPC_OPCODE_860 0x8000000000ull
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/* Opcode is only supported by Power9 architecture. */
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#define PPC_OPCODE_POWER9 0x20000000000ull
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#define PPC_OPCODE_POWER9 0x10000000000ull
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/* Opcode is supported by e200z4. */
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#define PPC_OPCODE_E200Z4 0x80000000000ull
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#define PPC_OPCODE_E200Z4 0x20000000000ull
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/* Disassemble to instructions matching later in the opcode table
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with fewer "mask" bits set rather than the earlist match. Fewer
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"mask" bits set imply a more general form of the opcode, in fact
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the underlying machine instruction. */
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#define PPC_OPCODE_RAW 0x100000000000ull
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#define PPC_OPCODE_RAW 0x40000000000ull
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/* A macro to extract the major opcode from an instruction. */
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#define PPC_OP(i) (((i) >> 26) & 0x3f)
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