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https://github.com/espressif/binutils-gdb.git
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2007-09-14 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_modrm_byte): Adjust indentation.
This commit is contained in:
@ -1,3 +1,7 @@
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2007-09-14 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (build_modrm_byte): Adjust indentation.
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2007-09-14 Michael Meissner <michael.meissner@amd.com>
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2007-09-14 Michael Meissner <michael.meissner@amd.com>
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Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
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Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
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Tony Linthicum <tony.linthicum@amd.com>
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Tony Linthicum <tony.linthicum@amd.com>
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@ -4476,10 +4476,10 @@ build_modrm_byte (void)
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op = i.drex.modrm_regmem;
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op = i.drex.modrm_regmem;
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else
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else
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{
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{
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for (op = 0; op < i.operands; op++)
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for (op = 0; op < i.operands; op++)
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if (operand_type_check (i.types[op], anymem))
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if (operand_type_check (i.types[op], anymem))
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break;
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break;
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assert (op < i.operands);
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assert (op < i.operands);
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}
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}
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default_seg = &ds;
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default_seg = &ds;
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@ -4686,35 +4686,36 @@ build_modrm_byte (void)
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}
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}
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else
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else
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{
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{
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for (op = 0; op < i.operands; op++)
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for (op = 0; op < i.operands; op++)
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if (i.types[op].bitfield.reg8
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if (i.types[op].bitfield.reg8
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|| i.types[op].bitfield.reg16
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|| i.types[op].bitfield.reg16
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|| i.types[op].bitfield.reg32
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|| i.types[op].bitfield.reg32
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|| i.types[op].bitfield.reg64
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|| i.types[op].bitfield.reg64
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|| i.types[op].bitfield.regmmx
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|| i.types[op].bitfield.regmmx
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|| i.types[op].bitfield.regxmm
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|| i.types[op].bitfield.regxmm
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|| i.types[op].bitfield.sreg2
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|| i.types[op].bitfield.sreg2
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|| i.types[op].bitfield.sreg3
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|| i.types[op].bitfield.sreg3
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|| i.types[op].bitfield.control
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|| i.types[op].bitfield.control
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|| i.types[op].bitfield.debug
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|| i.types[op].bitfield.debug
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|| i.types[op].bitfield.test)
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|| i.types[op].bitfield.test)
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break;
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break;
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assert (op < i.operands);
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assert (op < i.operands);
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/* If there is an extension opcode to put here, the
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/* If there is an extension opcode to put here, the
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register number must be put into the regmem field. */
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register number must be put into the regmem field. */
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if (i.tm.extension_opcode != None)
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if (i.tm.extension_opcode != None)
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{
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{
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i.rm.regmem = i.op[op].regs->reg_num;
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i.rm.regmem = i.op[op].regs->reg_num;
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if ((i.op[op].regs->reg_flags & RegRex) != 0)
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if ((i.op[op].regs->reg_flags & RegRex) != 0)
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i.rex |= REX_B;
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i.rex |= REX_B;
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}
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}
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else
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else
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{
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{
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i.rm.reg = i.op[op].regs->reg_num;
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i.rm.reg = i.op[op].regs->reg_num;
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if ((i.op[op].regs->reg_flags & RegRex) != 0)
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if ((i.op[op].regs->reg_flags & RegRex) != 0)
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i.rex |= REX_R;
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i.rex |= REX_R;
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}
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}
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}
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}
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/* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
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/* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
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