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x86/Intel: debug registers are named DRn

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%db<n> is an AT&T invention; the Intel documentation and MASM have only
ever specified DRn (in line with CRn and TRn). (In principle gas also
shouldn't accept the names in Intel mode, but at least for now I've kept
things as they are. Perhaps as a first step this should just be warned
about.)
This commit is contained in:
Jan Beulich
2020-07-14 10:43:38 +02:00
parent 78467458dd
commit bfbd943845
7 changed files with 19 additions and 8 deletions
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7
gas/ChangeLog
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@ -1,3 +1,10 @@
2020-07-14 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/intel.s: Use dr<N> instead of db<N>.
* testsuite/gas/i386/intel-intel.d: Disambiguate name.
* testsuite/gas/i386/intel.d,
testsuite/gas/i386/opcode-intel.d: Adjust expectations.
2020-07-14 Jan Beulich <jbeulich@suse.com> 2020-07-14 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/prefix.d: Adjust expectations. * testsuite/gas/i386/prefix.d: Adjust expectations.

4
gas/testsuite/gas/i386/intel-intel.d
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@ -260,9 +260,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 09 + wbinvd * [ ]*[a-f0-9]+: 0f 09 + wbinvd *
[ ]*[a-f0-9]+: 0f 0b + ud2 * [ ]*[a-f0-9]+: 0f 0b + ud2 *
[ ]*[a-f0-9]+: 0f 20 d0 + mov eax,cr2 [ ]*[a-f0-9]+: 0f 20 d0 + mov eax,cr2
[ ]*[a-f0-9]+: 0f 21 d0 + mov eax,db2 [ ]*[a-f0-9]+: 0f 21 d0 + mov eax,dr2
[ ]*[a-f0-9]+: 0f 22 d0 + mov cr2,eax [ ]*[a-f0-9]+: 0f 22 d0 + mov cr2,eax
[ ]*[a-f0-9]+: 0f 23 d0 + mov db2,eax [ ]*[a-f0-9]+: 0f 23 d0 + mov dr2,eax
[ ]*[a-f0-9]+: 0f 24 d0 + mov eax,tr2 [ ]*[a-f0-9]+: 0f 24 d0 + mov eax,tr2
[ ]*[a-f0-9]+: 0f 26 d0 + mov tr2,eax [ ]*[a-f0-9]+: 0f 26 d0 + mov tr2,eax
[ ]*[a-f0-9]+: 0f 30 + wrmsr * [ ]*[a-f0-9]+: 0f 30 + wrmsr *

2
gas/testsuite/gas/i386/intel.d
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@ -1,6 +1,6 @@
#as: -J #as: -J
#objdump: -dw #objdump: -dw
#name: i386 intel #name: i386 intel (AT&T disassembly)
#warning_output: intel.e #warning_output: intel.e
.*: +file format .* .*: +file format .*

4
gas/testsuite/gas/i386/intel.s
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@ -252,9 +252,9 @@ foo:
wbinvd wbinvd
ud2a ud2a
mov eax, cr2 mov eax, cr2
mov eax, db2 mov eax, dr2
mov cr2, eax mov cr2, eax
mov db2, eax mov dr2, eax
mov eax, tr2 mov eax, tr2
mov tr2, eax mov tr2, eax
wrmsr wrmsr

4
gas/testsuite/gas/i386/opcode-intel.d
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@ -257,9 +257,9 @@ Disassembly of section .text:
*[0-9a-f]+: 0f 09[ ]+wbinvd[ ]* *[0-9a-f]+: 0f 09[ ]+wbinvd[ ]*
*[0-9a-f]+: 0f 0b[ ]+ud2[ ]* *[0-9a-f]+: 0f 0b[ ]+ud2[ ]*
*[0-9a-f]+: 0f 20 d0[ ]+mov[ ]+eax,cr2 *[0-9a-f]+: 0f 20 d0[ ]+mov[ ]+eax,cr2
*[0-9a-f]+: 0f 21 d0[ ]+mov[ ]+eax,db2 *[0-9a-f]+: 0f 21 d0[ ]+mov[ ]+eax,dr2
*[0-9a-f]+: 0f 22 d0[ ]+mov[ ]+cr2,eax *[0-9a-f]+: 0f 22 d0[ ]+mov[ ]+cr2,eax
*[0-9a-f]+: 0f 23 d0[ ]+mov[ ]+db2,eax *[0-9a-f]+: 0f 23 d0[ ]+mov[ ]+dr2,eax
*[0-9a-f]+: 0f 24 d0[ ]+mov[ ]+eax,tr2 *[0-9a-f]+: 0f 24 d0[ ]+mov[ ]+eax,tr2
*[0-9a-f]+: 0f 26 d0[ ]+mov[ ]+tr2,eax *[0-9a-f]+: 0f 26 d0[ ]+mov[ ]+tr2,eax
*[0-9a-f]+: 0f 30[ ]+wrmsr[ ]* *[0-9a-f]+: 0f 30[ ]+wrmsr[ ]*

4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2020-07-14 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
2020-07-14 Jan Beulich <jbeulich@suse.com> 2020-07-14 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (OP_R, Rm): Delete. * i386-dis.c (OP_R, Rm): Delete.

2
opcodes/i386-dis.c
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@ -12787,7 +12787,7 @@ OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
else else
add = 0; add = 0;
if (intel_syntax) if (intel_syntax)
sprintf (scratchbuf, "db%d", modrm.reg + add); sprintf (scratchbuf, "dr%d", modrm.reg + add);
else else
sprintf (scratchbuf, "%%db%d", modrm.reg + add); sprintf (scratchbuf, "%%db%d", modrm.reg + add);
oappend (scratchbuf); oappend (scratchbuf);