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[ARC] Prefer NOP instead of MOV 0,0

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NOP and MOV 0,0 are having the same encoding. As MOV mnemonic is
located before NOP in the instruction table, the disassembler prints
MOV 0,0 for NOP. Reorder the instructions such that NOP is first.

gas/
2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/b.d: Update test.
	* testsuite/gas/arc/noargs_hs.d: Likewise.

opcode/
2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-tbl.h: Reorder NOP entry to be before MOV instructions.
This commit is contained in:
Claudiu Zissulescu
2017-04-25 17:07:00 +02:00
committed by claziss
parent d581dda881
commit be6a24d8ea
5 changed files with 17 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/b.d: Update test.
* testsuite/gas/arc/noargs_hs.d: Likewise.
2017-04-25 Maciej W. Rozycki <macro@imgtec.com> 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (md_convert_frag): Correct * config/tc-mips.c (md_convert_frag): Correct

8
gas/testsuite/gas/arc/b.d
View File

@ -35,12 +35,12 @@ Disassembly of section .text:
68: 0798 ffce bls -104 68: 0798 ffce bls -104
6c: 0794 ffcf bpnz -108 6c: 0794 ffcf bpnz -108
70: 0791 ffef b.d 0 <text_label> 70: 0791 ffef b.d 0 <text_label>
74: 264a 7000 mov 0,0 74: 264a 7000 nop
78: 0789 ffcf b 0 <text_label> 78: 0789 ffcf b 0 <text_label>
7c: 0785 ffef b.d 0 <text_label> 7c: 0785 ffef b.d 0 <text_label>
80: 264a 7000 mov 0,0 80: 264a 7000 nop
84: 077c ffe1 beq.d -132 84: 077c ffe1 beq.d -132
88: 264a 7000 mov 0,0 88: 264a 7000 nop
8c: 0774 ffc2 bne -140 8c: 0774 ffc2 bne -140
90: 0770 ffe6 bnc.d -144 90: 0770 ffe6 bnc.d -144
94: 264a 7000 mov 0,0 94: 264a 7000 nop

2
gas/testsuite/gas/arc/noargs_hs.d
View File

@ -14,7 +14,7 @@ Disassembly of section .text:
e: 246f 003f rtie e: 246f 003f rtie
12: 216f 003f sleep 0 12: 216f 003f sleep 0
16: 226f 103f dsync 16: 226f 103f dsync
1a: 264a 7000 mov 0,0 1a: 264a 7000 nop
1e: 78e0 nop_s 1e: 78e0 nop_s
20: 256f 003f brk 20: 256f 003f brk
24: 236f 003f sync 24: 236f 003f sync

4
opcodes/ChangeLog
View File

@ -1,3 +1,7 @@
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h: Reorder NOP entry to be before MOV instructions.
2017-04-25 Maciej W. Rozycki <macro@imgtec.com> 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
* mips-dis.c (print_mips_disassembler_options): Add * mips-dis.c (print_mips_disassembler_options): Add

6
opcodes/arc-tbl.h
View File

@ -10113,6 +10113,9 @@
/* minidl<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */ /* minidl<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */
{ "minidl", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, { "minidl", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
/* nop 00100110010010100111000000000000. */
{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
/* mov<.f> b,c 00100bbb00001010FBBBCCCCCCRRRRRR. */ /* mov<.f> b,c 00100bbb00001010FBBBCCCCCCRRRRRR. */
{ "mov", 0x200A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { RB, RC }, { C_F }}, { "mov", 0x200A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { RB, RC }, { C_F }},
@ -12702,9 +12705,6 @@
/* neg_s b,c 01111bbbccc10011. */ /* neg_s b,c 01111bbbccc10011. */
{ "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }}, { "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
/* nop 00100110010010100111000000000000. */
{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
/* nop_s 0111100011100000. */ /* nop_s 0111100011100000. */
{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, { "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},