Enable Intel PCONFIG instruction.

Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

This patch enables Intel PCONFIG instruction.

gas/
	* config/tc-i386.c (cpu_arch): Add .pconfig.
	* doc/c-i386.texi: Document .pconfig.
	* testsuite/gas/i386/i386.exp: Add PCONFIG tests.
	* testsuite/gas/i386/pconfig-intel.d: New test.
	* testsuite/gas/i386/pconfig.d: Likewise.
	* testsuite/gas/i386/pconfig.s: Likewise.
	* testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-pconfig.d: Likewise.
	* testsuite/gas/i386/x86-64-pconfig.s: Likewise.
opcodes/
	* i386-dis.c (enum): Add pconfig.
	* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
	(cpu_flags): Add CpuPCONFIG.
	* i386-opc.h (enum): Add CpuPCONFIG.
	(i386_cpu_flags): Add cpupconfig.
	* i386-opc.tbl: Add PCONFIG instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.

gas/ChangeLog

@@ -1,3 +1,15 @@
+2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
+
+	* config/tc-i386.c (cpu_arch): Add .pconfig.
+	* doc/c-i386.texi: Document .pconfig.
+	* testsuite/gas/i386/i386.exp: Add PCONFIG tests.
+	* testsuite/gas/i386/pconfig-intel.d: New test.
+	* testsuite/gas/i386/pconfig.d: Likewise.
+	* testsuite/gas/i386/pconfig.s: Likewise.
+	* testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise.
+	* testsuite/gas/i386/x86-64-pconfig.d: Likewise.
+	* testsuite/gas/i386/x86-64-pconfig.s: Likewise.
+
 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 
 	* config/tc-i386.c (cpu_arch): Add .wbnoinvd.

gas/config/tc-i386.c

@@ -1009,6 +1009,8 @@ static const arch_entry cpu_arch[] =
     CPU_VPCLMULQDQ_FLAGS, 0 },
   { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
     CPU_WBNOINVD_FLAGS, 0 },
+  { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
+    CPU_PCONFIG_FLAGS, 0 },
 };
 
 static const noarch_entry cpu_noarch[] =

gas/doc/c-i386.texi

@@ -230,6 +230,7 @@ accept various extension mnemonics.  For example,
 @code{mwaitx},
 @code{clzero},
 @code{wbnoinvd},
+@code{pconfig},
 @code{lwp},
 @code{fma4},
 @code{xop},
@@ -1241,7 +1242,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
 @item @samp{.avx512_bitalg}
 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
-@item @samp{.wbnoinvd}
+@item @samp{.wbnoinvd} @tab @samp{.pconfig}
 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}

gas/testsuite/gas/i386/i386.exp

@@ -415,6 +415,8 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "vpclmulqdq-intel"
     run_dump_test "wbnoinvd"
     run_dump_test "wbnoinvd-intel"
+    run_dump_test "pconfig"
+    run_dump_test "pconfig-intel"
     run_list_test "avx512vl-1" "-al"
     run_list_test "avx512vl-2" "-al"
     run_dump_test "fpu-bad"
@@ -884,6 +886,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-vpclmulqdq-intel"
     run_dump_test "x86-64-wbnoinvd"
     run_dump_test "x86-64-wbnoinvd-intel"
+    run_dump_test "x86-64-pconfig"
+    run_dump_test "x86-64-pconfig-intel"
     run_dump_test "x86-64-fence-as-lock-add-yes"
     run_dump_test "x86-64-fence-as-lock-add-no"
     run_dump_test "x86-64-pr20141"

gas/testsuite/gas/i386/pconfig-intel.d

@@ -0,0 +1,11 @@
+#objdump: -dwMintel
+#name: i386 PCONFIG (Intel disassembly)
+#source: pconfig.s
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*0f 01 c5[ 	]*pconfig[ 	]*
+#pass

gas/testsuite/gas/i386/pconfig.d

@@ -0,0 +1,11 @@
+#objdump: -dw
+#name: i386 PCONFIG insn
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*0f 01 c5[ 	]*pconfig[ 	]*
+#pass

gas/testsuite/gas/i386/pconfig.s

@@ -0,0 +1,5 @@
+# Check 32bit PCONFIG instructions.
+
+	.text
+_start:
+	pconfig

gas/testsuite/gas/i386/x86-64-pconfig-intel.d

@@ -0,0 +1,11 @@
+#objdump: -dwMintel
+#name: i386 PCONFIG (Intel disassembly)
+#source: pconfig.s
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*0f 01 c5[ 	]*pconfig[ 	]*
+#pass

gas/testsuite/gas/i386/x86-64-pconfig.d

@@ -0,0 +1,11 @@
+#objdump: -dw
+#name: i386 PCONFIG insn
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*0f 01 c5[ 	]*pconfig[ 	]*
+#pass

gas/testsuite/gas/i386/x86-64-pconfig.s

@@ -0,0 +1,5 @@
+# Check 64bit PCONFIG instructions.
+
+	.text
+_start:
+	pconfig

opcodes/ChangeLog

@@ -1,3 +1,14 @@
+2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
+
+	* i386-dis.c (enum): Add pconfig.
+	* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
+	(cpu_flags): Add CpuPCONFIG.
+	* i386-opc.h (enum): Add CpuPCONFIG.
+	(i386_cpu_flags): Add cpupconfig.
+	* i386-opc.tbl: Add PCONFIG instruction.
+	* i386-init.h: Regenerate.
+	* i386-tbl.h: Likewise.
+
 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 
 	* i386-dis.c (enum): Add PREFIX_0F09.

opcodes/i386-dis.c

@@ -12259,6 +12259,7 @@ static const struct dis386 rm_table[][8] = {
     { "vmlaunch",	{ Skip_MODRM }, 0 },
     { "vmresume",	{ Skip_MODRM }, 0 },
     { "vmxoff",		{ Skip_MODRM }, 0 },
+    { "pconfig",	{ Skip_MODRM }, 0 },
   },
   {
     /* RM_0F01_REG_1 */

opcodes/i386-gen.c

@@ -281,6 +281,8 @@ static initializer cpu_flag_init[] =
     "CpuVPCLMULQDQ" },
   { "CPU_WBNOINVD_FLAGS",
     "CpuWBNOINVD" },
+  { "CPU_PCONFIG_FLAGS",
+    "CpuPCONFIG" },
   { "CPU_ANY_X87_FLAGS",
     "CPU_ANY_287_FLAGS|Cpu8087" },
   { "CPU_ANY_287_FLAGS",
@@ -572,6 +574,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuVAES),
   BITFIELD (CpuVPCLMULQDQ),
   BITFIELD (CpuWBNOINVD),
+  BITFIELD (CpuPCONFIG),
   BITFIELD (CpuRegMMX),
   BITFIELD (CpuRegXMM),
   BITFIELD (CpuRegYMM),

opcodes/i386-opc.h

@@ -225,6 +225,8 @@ enum
   CpuVPCLMULQDQ,
   /* WBNOINVD instructions required */
   CpuWBNOINVD,
+  /* PCONFIG instructions required */
+  CpuPCONFIG,
   /* MMX register support required */
   CpuRegMMX,
   /* XMM register support required */
@@ -355,6 +357,7 @@ typedef union i386_cpu_flags
       unsigned int cpuvaes:1;
       unsigned int cpuvpclmulqdq:1;
       unsigned int cpuwbnoinvd:1;
+      unsigned int cpupconfig:1;
       unsigned int cpuregmmx:1;
       unsigned int cpuregxmm:1;
       unsigned int cpuregymm:1;

opcodes/i386-opc.tbl

@@ -6139,3 +6139,9 @@ notrack, 0, 0x3e, None, 1, CpuIBT, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld
 wbnoinvd, 0, 0xf30f09, None, 2, CpuWBNOINVD, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 
 // WBNOINVD instruction end.
+
+// PCONFIG instruction.
+
+pconfig, 0, 0x0f01c5, None, 3, CpuPCONFIG, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+
+// PCONFIG instruction end.