arc: Change max instruction length to 64-bits

The current handling for arc instructions longer than 32-bits is all
handled as a special case in both the assembler and disassembler.

The problem with this approach is that it leads to code duplication,
selecting a long instruction is exactly the same process as selecting a
short instruction, except over more bits, in both cases we select based
on bit comparison, and initial operand insertion and extraction.

This commit unifies both the long and short instruction worlds,
converting the core opcodes library from being largely 32-bit focused,
to being largely 64-bit focused.

The changes are, on the whole, not too much.  There's obviously a lot of
type changes but otherwise the bulk of the code just works.  Most of the
actual functional changes are to code that previously handled the longer
48 or 64 bit instructions.  The insert/extract handlers for these have
now been brought into line with the short instruction insert/extract
handlers.

All of the special case handling code that was previously added has now
been removed again.  Overall, this commit reduces the amount of code in
the arc assembler and disassembler.

gas/ChangeLog:

	* config/tc-arc.c (struct arc_insn): Change type of insn field.
	(md_number_to_chars_midend): Support 6- and 8-byte values.
	(emit_insn0): Update debug output.
	(find_opcode_match): Likewise.
	(build_fake_opcode_hash_entry): Delete.
	(find_special_case_long_opcode): Delete.
	(find_special_case): Remove long format special case handling.
	(insert_operand): Change instruction type and update debug print
	format.
	(assemble_insn): Change instruction type, update debug print
	formats, and remove unneeded assert.

include/ChangeLog:

	* opcode/arc.h (struct arc_opcode): Change type of opcode and mask
	fields.
	(struct arc_long_opcode): Delete.
	(struct arc_operand): Change types for insert and extract
	handlers.

opcodes/ChangeLog:

	* arc-dis.c (struct arc_operand_iterator): Remove all fields
	relating to long instruction processing, add new limm field.
	(OPCODE): Rename to...
	(OPCODE_32BIT_INSN): ...this.
	(OPCODE_AC): Delete.
	(skip_this_opcode): Handle different instruction lengths, update
	macro name.
	(special_flag_p): Update parameter type.
	(find_format_from_table): Update for more instruction lengths.
	(find_format_long_instructions): Delete.
	(find_format): Update for more instruction lengths.
	(arc_insn_length): Likewise.
	(extract_operand_value): Update for more instruction lengths.
	(operand_iterator_next): Remove code relating to long
	instructions.
	(arc_opcode_to_insn_type): New function.
	(print_insn_arc):Update for more instructions lengths.
	* arc-ext.c (extInstruction_t): Change argument type.
	* arc-ext.h (extInstruction_t): Change argument type.
	* arc-fxi.h: Change type unsigned to unsigned long long
	extensively throughout.
	* arc-nps400-tbl.h: Add long instructions taken from
	arc_long_opcodes table in arc-opc.c.
	* arc-opc.c: Update parameter types on insert/extract handlers.
	(arc_long_opcodes): Delete.
	(arc_num_long_opcodes): Delete.
	(arc_opcode_len): Update for more instruction lengths.

include/opcode/arc.h

@@ -116,13 +116,13 @@ struct arc_opcode
 
   /* The opcode itself.  Those bits which will be filled in with
      operands are zeroes.  */
-  unsigned opcode;
+  unsigned long long opcode;
 
   /* The opcode mask.  This is used by the disassembler.  This is a
      mask containing ones indicating those bits which must match the
      opcode field, and zeroes indicating those bits which need not
      match (and are presumably filled in by operands).  */
-  unsigned mask;
+  unsigned long long mask;
 
   /* One bit flags for the opcode.  These are primarily used to
      indicate specific processors and environments support the
@@ -146,30 +146,6 @@ struct arc_opcode
   unsigned char flags[MAX_INSN_FLGS + 1];
 };
 
-/* Structure used to describe 48 and 64 bit instructions.  */
-struct arc_long_opcode
-{
-  /* The base instruction is either 16 or 32 bits, and is described like a
-     normal instruction.  */
-  struct arc_opcode base_opcode;
-
-  /* The template value for the 32-bit LIMM extension.  Used by the
-     assembler and disassembler in the same way as the 'opcode' field of
-     'struct arc_opcode'.  */
-  unsigned limm_template;
-
-  /* The mask value for the 32-bit LIMM extension.  Used by the
-     disassembler just like the 'mask' field in 'struct arc_opcode'.  */
-  unsigned limm_mask;
-
-  /* Array of operand codes similar to the 'operands' array in 'struct
-     arc_opcode'.  These operands are used to fill in the LIMM value.  */
-  unsigned char operands[MAX_INSN_ARGS + 1];
-};
-
-extern const struct arc_long_opcode arc_long_opcodes[];
-extern const unsigned arc_num_long_opcodes;
-
 /* The table itself is sorted by major opcode number, and is otherwise
    in the order in which the disassembler should consider
    instructions.  */
@@ -262,7 +238,9 @@ struct arc_operand
      string (the operand will be inserted in any case).	 If the
      operand value is legal, *ERRMSG will be unchanged (most operands
      can accept any value).  */
-  unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
+  unsigned long long (*insert) (unsigned long long instruction,
+                                long long int op,
+                                const char **errmsg);
 
   /* Extraction function.  This is used by the disassembler.  To
      extract this operand type from an instruction, check this field.
@@ -281,7 +259,8 @@ struct arc_operand
      TRUE if this operand type can not actually be extracted from
      this operand (i.e., the instruction does not match).  If the
      operand is valid, *INVALID will not be changed.  */
-  int (*extract) (unsigned instruction, bfd_boolean *invalid);
+  long long int (*extract) (unsigned long long instruction,
+                            bfd_boolean *invalid);
 };
 
 /* Elements in the table are retrieved by indexing with values from