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[AArch64] Support id_mmfr4 system register

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2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
opcodes/
  * aarch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".

gas/testsuite
  * sysreg.d: Add id_mmfr4_el1, update expected output.
  * sysreg.s: Add id_mmfr4_el1.
This commit is contained in:
Matthew Wahab
2015-06-16 14:15:54 +01:00
committed by Jiong Wang
parent 56f4083249
commit bdfa8b951b
5 changed files with 23 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
gas/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
* sysreg.d: Add id_mmfr4_el1, update expected output.
* sysreg.s: Add id_mmfr4_el1.
2015-06-15 Renlin Li <renlin.li@arm.com> 2015-06-15 Renlin Li <renlin.li@arm.com>
* gas/aarch64/reloc-insn.s: Update test * gas/aarch64/reloc-insn.s: Update test

23
gas/testsuite/gas/aarch64/sysreg.d
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@ -17,14 +17,15 @@ Disassembly of section \.text:
24: d53801a0 mrs x0, id_mmfr1_el1 24: d53801a0 mrs x0, id_mmfr1_el1
28: d53801c0 mrs x0, id_mmfr2_el1 28: d53801c0 mrs x0, id_mmfr2_el1
2c: d53801e0 mrs x0, id_mmfr3_el1 2c: d53801e0 mrs x0, id_mmfr3_el1
30: d5380200 mrs x0, id_isar0_el1 30: d53802c0 mrs x0, id_mmfr4_el1
34: d5380220 mrs x0, id_isar1_el1 34: d5380200 mrs x0, id_isar0_el1
38: d5380240 mrs x0, id_isar2_el1 38: d5380220 mrs x0, id_isar1_el1
3c: d5380260 mrs x0, id_isar3_el1 3c: d5380240 mrs x0, id_isar2_el1
40: d5380280 mrs x0, id_isar4_el1 40: d5380260 mrs x0, id_isar3_el1
44: d53802a0 mrs x0, id_isar5_el1 44: d5380280 mrs x0, id_isar4_el1
48: d538cc00 mrs x0, s3_0_c12_c12_0 48: d53802a0 mrs x0, id_isar5_el1
4c: d5384600 mrs x0, s3_0_c4_c6_0 4c: d538cc00 mrs x0, s3_0_c12_c12_0
50: d5184600 msr s3_0_c4_c6_0, x0 50: d5384600 mrs x0, s3_0_c4_c6_0
54: d5310300 mrs x0, s2_1_c0_c3_0 54: d5184600 msr s3_0_c4_c6_0, x0
58: d5110300 msr s2_1_c0_c3_0, x0 58: d5310300 mrs x0, s2_1_c0_c3_0
5c: d5110300 msr s2_1_c0_c3_0, x0

1
gas/testsuite/gas/aarch64/sysreg.s
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@ -16,6 +16,7 @@
mrs x0, id_mmfr1_el1 mrs x0, id_mmfr1_el1
mrs x0, id_mmfr2_el1 mrs x0, id_mmfr2_el1
mrs x0, id_mmfr3_el1 mrs x0, id_mmfr3_el1
mrs x0, id_mmfr4_el1
mrs x0, id_isar0_el1 mrs x0, id_isar0_el1
mrs x0, id_isar1_el1 mrs x0, id_isar1_el1
mrs x0, id_isar2_el1 mrs x0, id_isar2_el1

4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
* arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com> 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
* arm-dis.c (print_insn_coprocessor): Avoid negative shift. * arm-dis.c (print_insn_coprocessor): Avoid negative shift.

1
opcodes/aarch64-opc.c
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@ -2772,6 +2772,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "id_mmfr1_el1", CPENC(3,0,C0,C1,5), 0 }, /* RO */ { "id_mmfr1_el1", CPENC(3,0,C0,C1,5), 0 }, /* RO */
{ "id_mmfr2_el1", CPENC(3,0,C0,C1,6), 0 }, /* RO */ { "id_mmfr2_el1", CPENC(3,0,C0,C1,6), 0 }, /* RO */
{ "id_mmfr3_el1", CPENC(3,0,C0,C1,7), 0 }, /* RO */ { "id_mmfr3_el1", CPENC(3,0,C0,C1,7), 0 }, /* RO */
{ "id_mmfr4_el1", CPENC(3,0,C0,C2,6), 0 }, /* RO */
{ "id_isar0_el1", CPENC(3,0,C0,C2,0), 0 }, /* RO */ { "id_isar0_el1", CPENC(3,0,C0,C2,0), 0 }, /* RO */
{ "id_isar1_el1", CPENC(3,0,C0,C2,1), 0 }, /* RO */ { "id_isar1_el1", CPENC(3,0,C0,C2,1), 0 }, /* RO */
{ "id_isar2_el1", CPENC(3,0,C0,C2,2), 0 }, /* RO */ { "id_isar2_el1", CPENC(3,0,C0,C2,2), 0 }, /* RO */