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include/opcode/

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* ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
	Renumber other PPC_OPCODE defines.
gas/
	* config/tc-ppc.c (ppc_set_cpu): Remove old opcode flags.
	(ppc_setup_opcodes): Likewise.  Simplify opcode selection.
opcodes/
	* ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
	* ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
	(PPC64, MFDEC2): Update.
	(NON32, NO371): Define.
	(powerpc_opcode): Update to not use old opcode flags, and avoid
	-m601 duplicates.
This commit is contained in:
Alan Modra
2010-07-03 06:51:56 +00:00
parent 21375995bd
commit bdc70b4a03
7 changed files with 135 additions and 157 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2010-07-03 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (ppc_set_cpu): Remove old opcode flags.
(ppc_setup_opcodes): Likewise. Simplify opcode selection.
2010-07-02 DJ Delorie <dj@redhat.com> 2010-07-02 DJ Delorie <dj@redhat.com>
* config/tc-rx.h (md_do_align): New. * config/tc-rx.h (md_do_align): New.

21
gas/config/tc-ppc.c
View File

@ -1251,16 +1251,16 @@ ppc_set_cpu (void)
if ((ppc_cpu & ~PPC_OPCODE_ANY) == 0) if ((ppc_cpu & ~PPC_OPCODE_ANY) == 0)
{ {
if (ppc_obj64) if (ppc_obj64)
ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64; ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_64;
else if (strncmp (default_os, "aix", 3) == 0 else if (strncmp (default_os, "aix", 3) == 0
&& default_os[3] >= '4' && default_os[3] <= '9') && default_os[3] >= '4' && default_os[3] <= '9')
ppc_cpu |= PPC_OPCODE_COMMON | PPC_OPCODE_32; ppc_cpu |= PPC_OPCODE_COMMON;
else if (strncmp (default_os, "aix3", 4) == 0) else if (strncmp (default_os, "aix3", 4) == 0)
ppc_cpu |= PPC_OPCODE_POWER | PPC_OPCODE_32; ppc_cpu |= PPC_OPCODE_POWER;
else if (strcmp (default_cpu, "rs6000") == 0) else if (strcmp (default_cpu, "rs6000") == 0)
ppc_cpu |= PPC_OPCODE_POWER | PPC_OPCODE_32; ppc_cpu |= PPC_OPCODE_POWER;
else if (strncmp (default_cpu, "powerpc", 7) == 0) else if (strncmp (default_cpu, "powerpc", 7) == 0)
ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32; ppc_cpu |= PPC_OPCODE_PPC;
else else
as_fatal (_("Unknown default cpu = %s, os = %s"), as_fatal (_("Unknown default cpu = %s, os = %s"),
default_cpu, default_os); default_cpu, default_os);
@ -1473,11 +1473,7 @@ ppc_setup_opcodes (void)
} }
} }
if ((op->flags & ppc_cpu & ~(PPC_OPCODE_32 | PPC_OPCODE_64)) != 0 if ((ppc_cpu & op->flags) != 0
&& ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == 0
|| ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64))
== (ppc_cpu & (PPC_OPCODE_32 | PPC_OPCODE_64)))
|| (ppc_cpu & PPC_OPCODE_64_BRIDGE) != 0)
&& !(ppc_cpu & op->deprecated)) && !(ppc_cpu & op->deprecated))
{ {
const char *retval; const char *retval;
@ -1485,11 +1481,6 @@ ppc_setup_opcodes (void)
retval = hash_insert (ppc_hash, op->name, (void *) op); retval = hash_insert (ppc_hash, op->name, (void *) op);
if (retval != NULL) if (retval != NULL)
{ {
/* Ignore Power duplicates for -m601. */
if ((ppc_cpu & PPC_OPCODE_601) != 0
&& (op->flags & PPC_OPCODE_POWER) != 0)
continue;
as_bad (_("duplicate instruction %s"), as_bad (_("duplicate instruction %s"),
op->name); op->name);
bad_insn = TRUE; bad_insn = TRUE;

5
include/opcode/ChangeLog
View File

@ -1,3 +1,8 @@
2010-07-03 Alan Modra <amodra@gmail.com>
* ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
Renumber other PPC_OPCODE defines.
2010-07-03 Alan Modra <amodra@gmail.com> 2010-07-03 Alan Modra <amodra@gmail.com>
* ppc.h (PPC_OPCODE_COMMON): Expand comment. * ppc.h (PPC_OPCODE_COMMON): Expand comment.

73
include/opcode/ppc.h
View File

@ -77,111 +77,102 @@ extern const int powerpc_num_opcodes;
/* Opcode is defined for the POWER2 (Rios 2) architecture. */ /* Opcode is defined for the POWER2 (Rios 2) architecture. */
#define PPC_OPCODE_POWER2 4 #define PPC_OPCODE_POWER2 4
/* Opcode is only defined on 32 bit architectures. */
#define PPC_OPCODE_32 8
/* Opcode is only defined on 64 bit architectures. */
#define PPC_OPCODE_64 0x10
/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
but it also supports many additional POWER instructions. */ but it also supports many additional POWER instructions. */
#define PPC_OPCODE_601 0x20 #define PPC_OPCODE_601 8
/* Opcode is supported in both the Power and PowerPC architectures /* Opcode is supported in both the Power and PowerPC architectures
(ie, compiler's -mcpu=common or assembler's -mcom). More than just (ie, compiler's -mcpu=common or assembler's -mcom). More than just
the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
and PPC_OPCODE_POWER2 because many instructions changed mnemonics and PPC_OPCODE_POWER2 because many instructions changed mnemonics
between POWER and POWERPC. */ between POWER and POWERPC. */
#define PPC_OPCODE_COMMON 0x40 #define PPC_OPCODE_COMMON 0x10
/* Opcode is supported for any Power or PowerPC platform (this is /* Opcode is supported for any Power or PowerPC platform (this is
for the assembler's -many option, and it eliminates duplicates). */ for the assembler's -many option, and it eliminates duplicates). */
#define PPC_OPCODE_ANY 0x80 #define PPC_OPCODE_ANY 0x20
/* Opcode is only defined on 64 bit architectures. */
#define PPC_OPCODE_64 0x40
/* Opcode is supported as part of the 64-bit bridge. */ /* Opcode is supported as part of the 64-bit bridge. */
#define PPC_OPCODE_64_BRIDGE 0x100 #define PPC_OPCODE_64_BRIDGE 0x80
/* Opcode is supported by Altivec Vector Unit */ /* Opcode is supported by Altivec Vector Unit */
#define PPC_OPCODE_ALTIVEC 0x200 #define PPC_OPCODE_ALTIVEC 0x100
/* Opcode is supported by PowerPC 403 processor. */ /* Opcode is supported by PowerPC 403 processor. */
#define PPC_OPCODE_403 0x400 #define PPC_OPCODE_403 0x200
/* Opcode is supported by PowerPC BookE processor. */ /* Opcode is supported by PowerPC BookE processor. */
#define PPC_OPCODE_BOOKE 0x800 #define PPC_OPCODE_BOOKE 0x400
/* Opcode is only supported by 64-bit PowerPC BookE processor. */
#define PPC_OPCODE_BOOKE64 0x1000
/* Opcode is supported by PowerPC 440 processor. */ /* Opcode is supported by PowerPC 440 processor. */
#define PPC_OPCODE_440 0x2000 #define PPC_OPCODE_440 0x800
/* Opcode is only supported by Power4 architecture. */ /* Opcode is only supported by Power4 architecture. */
#define PPC_OPCODE_POWER4 0x4000 #define PPC_OPCODE_POWER4 0x1000
/* Opcode is only supported by Power7 architecture. */ /* Opcode is only supported by Power7 architecture. */
#define PPC_OPCODE_POWER7 0x8000 #define PPC_OPCODE_POWER7 0x2000
/* Opcode is only supported by POWERPC Classic architecture. */
#define PPC_OPCODE_CLASSIC 0x10000
/* Opcode is only supported by e500x2 Core. */ /* Opcode is only supported by e500x2 Core. */
#define PPC_OPCODE_SPE 0x20000 #define PPC_OPCODE_SPE 0x4000
/* Opcode is supported by e500x2 Integer select APU. */ /* Opcode is supported by e500x2 Integer select APU. */
#define PPC_OPCODE_ISEL 0x40000 #define PPC_OPCODE_ISEL 0x8000
/* Opcode is an e500 SPE floating point instruction. */ /* Opcode is an e500 SPE floating point instruction. */
#define PPC_OPCODE_EFS 0x80000 #define PPC_OPCODE_EFS 0x10000
/* Opcode is supported by branch locking APU. */ /* Opcode is supported by branch locking APU. */
#define PPC_OPCODE_BRLOCK 0x100000 #define PPC_OPCODE_BRLOCK 0x20000
/* Opcode is supported by performance monitor APU. */ /* Opcode is supported by performance monitor APU. */
#define PPC_OPCODE_PMR 0x200000 #define PPC_OPCODE_PMR 0x40000
/* Opcode is supported by cache locking APU. */ /* Opcode is supported by cache locking APU. */
#define PPC_OPCODE_CACHELCK 0x400000 #define PPC_OPCODE_CACHELCK 0x80000
/* Opcode is supported by machine check APU. */ /* Opcode is supported by machine check APU. */
#define PPC_OPCODE_RFMCI 0x800000 #define PPC_OPCODE_RFMCI 0x100000
/* Opcode is only supported by Power5 architecture. */ /* Opcode is only supported by Power5 architecture. */
#define PPC_OPCODE_POWER5 0x1000000 #define PPC_OPCODE_POWER5 0x200000
/* Opcode is supported by PowerPC e300 family. */ /* Opcode is supported by PowerPC e300 family. */
#define PPC_OPCODE_E300 0x2000000 #define PPC_OPCODE_E300 0x400000
/* Opcode is only supported by Power6 architecture. */ /* Opcode is only supported by Power6 architecture. */
#define PPC_OPCODE_POWER6 0x4000000 #define PPC_OPCODE_POWER6 0x800000
/* Opcode is only supported by PowerPC Cell family. */ /* Opcode is only supported by PowerPC Cell family. */
#define PPC_OPCODE_CELL 0x8000000 #define PPC_OPCODE_CELL 0x1000000
/* Opcode is supported by CPUs with paired singles support. */ /* Opcode is supported by CPUs with paired singles support. */
#define PPC_OPCODE_PPCPS 0x10000000 #define PPC_OPCODE_PPCPS 0x2000000
/* Opcode is supported by Power E500MC */ /* Opcode is supported by Power E500MC */
#define PPC_OPCODE_E500MC 0x20000000 #define PPC_OPCODE_E500MC 0x4000000
/* Opcode is supported by PowerPC 405 processor. */ /* Opcode is supported by PowerPC 405 processor. */
#define PPC_OPCODE_405 0x40000000 #define PPC_OPCODE_405 0x8000000
/* Opcode is supported by Vector-Scalar (VSX) Unit */ /* Opcode is supported by Vector-Scalar (VSX) Unit */
#define PPC_OPCODE_VSX 0x80000000 #define PPC_OPCODE_VSX 0x10000000
/* Opcode is supported by A2. */ /* Opcode is supported by A2. */
#define PPC_OPCODE_A2 0x100000000ULL #define PPC_OPCODE_A2 0x20000000
/* Opcode is supported by PowerPC 476 processor. */ /* Opcode is supported by PowerPC 476 processor. */
#define PPC_OPCODE_476 0x200000000ULL #define PPC_OPCODE_476 0x40000000
/* Opcode is supported by AppliedMicro Titan core */ /* Opcode is supported by AppliedMicro Titan core */
#define PPC_OPCODE_TITAN 0x400000000ULL #define PPC_OPCODE_TITAN 0x80000000
/* Opcode which is supported by the e500 family */ /* Opcode which is supported by the e500 family */
#define PPC_OPCODE_E500 0x800000000ULL #define PPC_OPCODE_E500 0x100000000ull
/* A macro to extract the major opcode from an instruction. */ /* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f) #define PPC_OP(i) (((i) >> 26) & 0x3f)

9
opcodes/ChangeLog
View File

@ -1,3 +1,12 @@
2010-07-03 Alan Modra <amodra@gmail.com>
* ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
* ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
(PPC64, MFDEC2): Update.
(NON32, NO371): Define.
(powerpc_opcode): Update to not use old opcode flags, and avoid
-m601 duplicates.
2010-07-03 DJ Delorie <dj@delorie.com> 2010-07-03 DJ Delorie <dj@delorie.com>
* m32c-ibld.c: Regenerate. * m32c-ibld.c: Regenerate.

142
opcodes/ppc-dis.c
View File

@ -50,64 +50,55 @@ struct ppc_mopt {
}; };
struct ppc_mopt ppc_opts[] = { struct ppc_mopt ppc_opts[] = {
{ "403", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_403 { "403", (PPC_OPCODE_PPC | PPC_OPCODE_403),
| PPC_OPCODE_32),
0 }, 0 },
{ "405", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_403 { "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
| PPC_OPCODE_405 | PPC_OPCODE_32),
0 }, 0 },
{ "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
0 }, 0 },
{ "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
0 }, 0 },
{ "476", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
| PPC_OPCODE_440 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
| PPC_OPCODE_POWER5),
0 }, 0 },
{ "601", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_601 { "601", (PPC_OPCODE_PPC | PPC_OPCODE_601),
| PPC_OPCODE_32),
0 }, 0 },
{ "603", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32), { "603", (PPC_OPCODE_PPC),
0 }, 0 },
{ "604", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32), { "604", (PPC_OPCODE_PPC),
0 }, 0 },
{ "620", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64), { "620", (PPC_OPCODE_PPC | PPC_OPCODE_64),
0 }, 0 },
{ "7400", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC { "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
| PPC_OPCODE_32),
0 }, 0 },
{ "7410", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC { "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
| PPC_OPCODE_32),
0 }, 0 },
{ "7450", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
| PPC_OPCODE_32),
0 }, 0 },
{ "7455", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC { "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
| PPC_OPCODE_32),
0 }, 0 },
{ "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS) { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
, 0 }, , 0 },
{ "a2", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
| PPC_OPCODE_64 | PPC_OPCODE_A2), | PPC_OPCODE_A2),
0 }, 0 },
{ "altivec", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC), { "altivec", (PPC_OPCODE_PPC),
PPC_OPCODE_ALTIVEC }, PPC_OPCODE_ALTIVEC },
{ "any", 0, { "any", 0,
PPC_OPCODE_ANY }, PPC_OPCODE_ANY },
{ "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32), { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
0 }, 0 },
{ "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32), { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
0 }, 0 },
{ "cell", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC), | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
0 }, 0 },
{ "com", (PPC_OPCODE_COMMON | PPC_OPCODE_32), { "com", (PPC_OPCODE_COMMON),
0 }, 0 },
{ "e300", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32 { "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300),
| PPC_OPCODE_E300),
0 }, 0 },
{ "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
@ -130,62 +121,55 @@ struct ppc_mopt ppc_opts[] = {
0 }, 0 },
{ "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), { "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
0 }, 0 },
{ "power4", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64 { "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
| PPC_OPCODE_POWER4),
0 }, 0 },
{ "power5", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5), | PPC_OPCODE_POWER5),
0 }, 0 },
{ "power6", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
0 },
{ "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC), | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 }, 0 },
{ "power7", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL { "ppc", (PPC_OPCODE_PPC),
| PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX),
0 }, 0 },
{ "ppc", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32), { "ppc32", (PPC_OPCODE_PPC),
0 }, 0 },
{ "ppc32", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32), { "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64),
0 }, 0 },
{ "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64), { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
0 },
{ "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64_BRIDGE
| PPC_OPCODE_64),
0 }, 0 },
{ "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS), { "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
0 }, 0 },
{ "pwr", (PPC_OPCODE_POWER | PPC_OPCODE_32), { "pwr", (PPC_OPCODE_POWER),
0 }, 0 },
{ "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_32), { "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
0 }, 0 },
{ "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64 { "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
| PPC_OPCODE_POWER4),
0 }, 0 },
{ "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5), | PPC_OPCODE_POWER5),
0 }, 0 },
{ "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5), | PPC_OPCODE_POWER5),
0 }, 0 },
{ "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
0 },
{ "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC), | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 }, 0 },
{ "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL { "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
| PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX),
0 },
{ "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_32),
0 }, 0 },
{ "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), { "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
PPC_OPCODE_SPE }, PPC_OPCODE_SPE },
{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
| PPC_OPCODE_PMR | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN), | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
0 }, 0 },
{ "vsx", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC), { "vsx", (PPC_OPCODE_PPC),
PPC_OPCODE_VSX }, PPC_OPCODE_VSX },
}; };
@ -243,15 +227,9 @@ powerpc_init_dialect (struct disassemble_info *info)
if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0) if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0)
dialect = new_cpu; dialect = new_cpu;
else if (strcmp (arg, "32") == 0) else if (strcmp (arg, "32") == 0)
{ dialect &= ~PPC_OPCODE_64;
dialect &= ~PPC_OPCODE_64;
dialect |= PPC_OPCODE_32;
}
else if (strcmp (arg, "64") == 0) else if (strcmp (arg, "64") == 0)
{ dialect |= PPC_OPCODE_64;
dialect |= PPC_OPCODE_64;
dialect &= ~PPC_OPCODE_32;
}
else else
fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg); fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
@ -260,15 +238,15 @@ powerpc_init_dialect (struct disassemble_info *info)
arg = end; arg = end;
} }
if ((dialect & ~(PPC_OPCODE_32 | PPC_OPCODE_64)) == 0) if ((dialect & ~PPC_OPCODE_64) == 0)
{ {
if (info->mach == bfd_mach_ppc64) if (info->mach == bfd_mach_ppc64)
dialect |= PPC_OPCODE_64; dialect |= PPC_OPCODE_64;
else else
dialect |= PPC_OPCODE_32; dialect &= ~PPC_OPCODE_64;
/* Choose a reasonable default. */ /* Choose a reasonable default. */
dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_CLASSIC dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601
| PPC_OPCODE_601 | PPC_OPCODE_ALTIVEC); | PPC_OPCODE_ALTIVEC);
} }
info->private_data = priv; info->private_data = priv;

37
opcodes/ppc-opc.c
View File

@ -1908,8 +1908,9 @@ extract_dm (unsigned long insn,
#define POWER6 PPC_OPCODE_POWER6 #define POWER6 PPC_OPCODE_POWER6
#define POWER7 PPC_OPCODE_POWER7 #define POWER7 PPC_OPCODE_POWER7
#define CELL PPC_OPCODE_CELL #define CELL PPC_OPCODE_CELL
#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_PPCPS \
| PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
#define PPC403 PPC_OPCODE_403 #define PPC403 PPC_OPCODE_403
#define PPC405 PPC_OPCODE_405 #define PPC405 PPC_OPCODE_405
#define PPC440 PPC_OPCODE_440 #define PPC440 PPC_OPCODE_440
@ -1925,15 +1926,13 @@ extract_dm (unsigned long insn,
#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
#define MFDEC1 PPC_OPCODE_POWER #define MFDEC1 PPC_OPCODE_POWER
#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
#define BOOKE PPC_OPCODE_BOOKE #define BOOKE PPC_OPCODE_BOOKE
#define CLASSIC PPC_OPCODE_CLASSIC #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
#define PPCE300 PPC_OPCODE_E300 #define PPCE300 PPC_OPCODE_E300
#define PPCSPE PPC_OPCODE_SPE #define PPCSPE PPC_OPCODE_SPE
#define PPCISEL PPC_OPCODE_ISEL #define PPCISEL PPC_OPCODE_ISEL
@ -2622,12 +2621,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}}, {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}},
{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}}, {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}},
{"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}}, {"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}},
{"cmpli", OP(10), OP_MASK, PWRCOM, PPCNONE, {BF, RA, UI}}, {"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UI}},
{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}}, {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}},
{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}}, {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}},
{"cmpi", OP(11), OP_MASK, PPC, PPCNONE, {BF, L, RA, SI}}, {"cmpi", OP(11), OP_MASK, PPC, PPCNONE, {BF, L, RA, SI}},
{"cmpi", OP(11), OP_MASK, PWRCOM, PPCNONE, {BF, RA, SI}}, {"cmpi", OP(11), OP_MASK, PWRCOM, PPC, {BF, RA, SI}},
{"addic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, {"addic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
{"ai", OP(12), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, {"ai", OP(12), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
@ -3429,7 +3428,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}}, {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}}, {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
{"cmp", X(31,0), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}}, {"cmp", X(31,0), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}},
{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPCNONE, {BF, RA, RB}}, {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
@ -3530,7 +3529,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}}, {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}}, {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
{"cmpl", X(31,32), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}}, {"cmpl", X(31,32), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}},
{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPCNONE, {BF, RA, RB}}, {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
{"lvsr", X(31,38), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, {"lvsr", X(31,38), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
{"lvehx", X(31,39), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, {"lvehx", X(31,39), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
@ -3726,7 +3725,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE, {RB}}, {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE, {RB}},
{"mtsr", X(31,210), XRB_MASK|(1<<20), COM32, TITAN, {SR, RS}}, {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
{"eratwe", X(31,211), X_MASK, PPCA2, PPCNONE, {RS, RA, WS}}, {"eratwe", X(31,211), X_MASK, PPCA2, PPCNONE, {RS, RA, WS}},
@ -3769,8 +3768,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE, {RB}}, {"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE, {RB}},
{"mtsrin", X(31,242), XRA_MASK, PPC32, TITAN, {RS, RB}}, {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
{"mtsri", X(31,242), XRA_MASK, POWER32, PPCNONE, {RS, RB}}, {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}}, {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}},
{"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA, RB, CT}}, {"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA, RB, CT}},
@ -3893,7 +3892,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}}, {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}},
{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}}, {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}}, {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2|TITAN, PPCNONE, {RT}}, {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, PPCNONE, {RT}}, {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, PPCNONE, {RT}},
{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}}, {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}}, {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}},
@ -4097,9 +4096,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"tlbia", X(31,370), 0xffffffff, PPC, TITAN, {0}}, {"tlbia", X(31,370), 0xffffffff, PPC, TITAN, {0}},
{"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, PPCNONE, {RT}}, {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371, {RT}},
{"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, PPCNONE, {RT}}, {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371, {RT}},
{"mftb", X(31,371), X_MASK, CLASSIC|PPCA2, POWER7, {RT, TBR}}, {"mftb", X(31,371), X_MASK, PPC|PPCA2, NO371|POWER7, {RT, TBR}},
{"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}}, {"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
@ -4465,7 +4464,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, {"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
{"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, TITAN, {RT, SR}}, {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
{"lswi", X(31,597), X_MASK, PPCCOM, PPCNONE, {RT, RA0, NB}}, {"lswi", X(31,597), X_MASK, PPCCOM, PPCNONE, {RT, RA0, NB}},
{"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}}, {"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}},
@ -4514,7 +4513,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
{"mfsrin", X(31,659), XRA_MASK, PPC32, TITAN, {RT, RB}}, {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RS, RA0, RB}}, {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RS, RA0, RB}},