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[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions
This patch updates the Store allocation tags instructions in Armv8.5-A Memory Tagging Extension. This is part of the changes that have been introduced recently in the 00bet10 release All of these instructions have an updated register operand (Xt -> <Xt|SP>) - STG <Xt|SP>, [<Xn|SP>, #<simm>] - STG <Xt|SP>, [<Xn|SP>, #<simm>]! - STG <Xt|SP>, [<Xn|SP>], #<simm> - STZG <Xt|SP>, [<Xn|SP>, #<simm>] - STZG <Xt|SP>, [<Xn|SP>, #<simm>]! - STZG <Xt|SP>, [<Xn|SP>], #<simm> - ST2G <Xt|SP>, [<Xn|SP>, #<simm>] - ST2G <Xt|SP>, [<Xn|SP>, #<simm>]! - ST2G <Xt|SP>, [<Xn|SP>], #<simm> - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>] - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]! - STZ2G <Xt|SP>, [<Xn|SP>], #<simm> In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has the same field as FLD_Rt but follows other semantics of Rn_SP. *** gas/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (process_omitted_operand): Add case for AARCH64_OPND_Rt_SP. (parse_operands): Likewise. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP. *** opcodes/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_print_operand): Add case for AARCH64_OPND_Rt_SP. (verify_constraints): Likewise. * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions to accept Rt|SP as first operand. (AARCH64_OPERANDS): Add new Rt_SP. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
This commit is contained in:
@ -1,3 +1,13 @@
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2019-04-11 Sudakshina Das <sudi.das@arm.com>
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* config/tc-aarch64.c (process_omitted_operand): Add case for
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AARCH64_OPND_Rt_SP.
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(parse_operands): Likewise.
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* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
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* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
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* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
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* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
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2019-04-11 Sudakshina Das <sudi.das@arm.com>
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2019-04-11 Sudakshina Das <sudi.das@arm.com>
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* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.
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* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.
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@ -5135,6 +5135,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
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case AARCH64_OPND_Rm:
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case AARCH64_OPND_Rm:
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case AARCH64_OPND_Rt:
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case AARCH64_OPND_Rt:
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case AARCH64_OPND_Rt2:
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case AARCH64_OPND_Rt2:
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case AARCH64_OPND_Rt_SP:
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case AARCH64_OPND_Rs:
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case AARCH64_OPND_Rs:
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case AARCH64_OPND_Ra:
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case AARCH64_OPND_Ra:
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case AARCH64_OPND_Rt_SYS:
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case AARCH64_OPND_Rt_SYS:
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@ -5511,6 +5512,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_Rd_SP:
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case AARCH64_OPND_Rd_SP:
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case AARCH64_OPND_Rn_SP:
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case AARCH64_OPND_Rn_SP:
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case AARCH64_OPND_Rt_SP:
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case AARCH64_OPND_SVE_Rn_SP:
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case AARCH64_OPND_SVE_Rn_SP:
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case AARCH64_OPND_Rm_SP:
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case AARCH64_OPND_Rm_SP:
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po_int_reg_or_fail (REG_TYPE_R_SP);
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po_int_reg_or_fail (REG_TYPE_R_SP);
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@ -57,64 +57,64 @@ Disassembly of section \.text:
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.*: badf001f cmpp x0, sp
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.*: badf001f cmpp x0, sp
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.*: d9200800 stg x0, \[x0\]
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.*: d9200800 stg x0, \[x0\]
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.*: d9200b60 stg x0, \[x27\]
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.*: d9200b60 stg x0, \[x27\]
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.*: d920081f stg xzr, \[x0\]
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.*: d920081f stg sp, \[x0\]
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.*: d93fb81b stg x27, \[x0, #-80\]
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.*: d93fb81b stg x27, \[x0, #-80\]
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.*: d9200c00 stg x0, \[x0, #0\]!
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.*: d9200c00 stg x0, \[x0, #0\]!
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.*: d9200c1f stg xzr, \[x0, #0\]!
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.*: d9200c1f stg sp, \[x0, #0\]!
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.*: d920ac1b stg x27, \[x0, #160\]!
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.*: d920ac1b stg x27, \[x0, #160\]!
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.*: d9200400 stg x0, \[x0\], #0
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.*: d9200400 stg x0, \[x0\], #0
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.*: d920041f stg xzr, \[x0\], #0
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.*: d920041f stg sp, \[x0\], #0
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.*: d93a641b stg x27, \[x0\], #-1440
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.*: d93a641b stg x27, \[x0\], #-1440
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.*: d92ffbe0 stg x0, \[sp, #4080\]
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.*: d92ffbe0 stg x0, \[sp, #4080\]
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.*: d92ffbff stg xzr, \[sp, #4080\]
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.*: d92ffbff stg sp, \[sp, #4080\]
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.*: d9300bfb stg x27, \[sp, #-4096\]
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.*: d9300bfb stg x27, \[sp, #-4096\]
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.*: d92fffe0 stg x0, \[sp, #4080\]!
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.*: d92fffe0 stg x0, \[sp, #4080\]!
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.*: d93007ff stg xzr, \[sp\], #-4096
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.*: d93007ff stg sp, \[sp\], #-4096
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.*: d9600800 stzg x0, \[x0\]
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.*: d9600800 stzg x0, \[x0\]
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.*: d9600b60 stzg x0, \[x27\]
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.*: d9600b60 stzg x0, \[x27\]
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.*: d960081f stzg xzr, \[x0\]
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.*: d960081f stzg sp, \[x0\]
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.*: d97fb81b stzg x27, \[x0, #-80\]
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.*: d97fb81b stzg x27, \[x0, #-80\]
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.*: d9600c00 stzg x0, \[x0, #0\]!
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.*: d9600c00 stzg x0, \[x0, #0\]!
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.*: d9600c1f stzg xzr, \[x0, #0\]!
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.*: d9600c1f stzg sp, \[x0, #0\]!
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.*: d960ac1b stzg x27, \[x0, #160\]!
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.*: d960ac1b stzg x27, \[x0, #160\]!
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.*: d9600400 stzg x0, \[x0\], #0
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.*: d9600400 stzg x0, \[x0\], #0
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.*: d960041f stzg xzr, \[x0\], #0
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.*: d960041f stzg sp, \[x0\], #0
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.*: d97a641b stzg x27, \[x0\], #-1440
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.*: d97a641b stzg x27, \[x0\], #-1440
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.*: d96ffbe0 stzg x0, \[sp, #4080\]
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.*: d96ffbe0 stzg x0, \[sp, #4080\]
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.*: d96ffbff stzg xzr, \[sp, #4080\]
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.*: d96ffbff stzg sp, \[sp, #4080\]
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.*: d9700bfb stzg x27, \[sp, #-4096\]
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.*: d9700bfb stzg x27, \[sp, #-4096\]
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.*: d96fffe0 stzg x0, \[sp, #4080\]!
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.*: d96fffe0 stzg x0, \[sp, #4080\]!
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.*: d97007ff stzg xzr, \[sp\], #-4096
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.*: d97007ff stzg sp, \[sp\], #-4096
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.*: d9a00800 st2g x0, \[x0\]
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.*: d9a00800 st2g x0, \[x0\]
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.*: d9a00b60 st2g x0, \[x27\]
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.*: d9a00b60 st2g x0, \[x27\]
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.*: d9a0081f st2g xzr, \[x0\]
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.*: d9a0081f st2g sp, \[x0\]
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.*: d9bfb81b st2g x27, \[x0, #-80\]
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.*: d9bfb81b st2g x27, \[x0, #-80\]
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.*: d9a00c00 st2g x0, \[x0, #0\]!
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.*: d9a00c00 st2g x0, \[x0, #0\]!
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.*: d9a00c1f st2g xzr, \[x0, #0\]!
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.*: d9a00c1f st2g sp, \[x0, #0\]!
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.*: d9a0ac1b st2g x27, \[x0, #160\]!
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.*: d9a0ac1b st2g x27, \[x0, #160\]!
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.*: d9a00400 st2g x0, \[x0\], #0
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.*: d9a00400 st2g x0, \[x0\], #0
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.*: d9a0041f st2g xzr, \[x0\], #0
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.*: d9a0041f st2g sp, \[x0\], #0
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.*: d9ba641b st2g x27, \[x0\], #-1440
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.*: d9ba641b st2g x27, \[x0\], #-1440
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.*: d9affbe0 st2g x0, \[sp, #4080\]
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.*: d9affbe0 st2g x0, \[sp, #4080\]
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.*: d9affbff st2g xzr, \[sp, #4080\]
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.*: d9affbff st2g sp, \[sp, #4080\]
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.*: d9b00bfb st2g x27, \[sp, #-4096\]
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.*: d9b00bfb st2g x27, \[sp, #-4096\]
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.*: d9afffe0 st2g x0, \[sp, #4080\]!
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.*: d9afffe0 st2g x0, \[sp, #4080\]!
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.*: d9b007ff st2g xzr, \[sp\], #-4096
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.*: d9b007ff st2g sp, \[sp\], #-4096
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.*: d9e00800 stz2g x0, \[x0\]
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.*: d9e00800 stz2g x0, \[x0\]
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.*: d9e00b60 stz2g x0, \[x27\]
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.*: d9e00b60 stz2g x0, \[x27\]
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.*: d9e0081f stz2g xzr, \[x0\]
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.*: d9e0081f stz2g sp, \[x0\]
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.*: d9ffb81b stz2g x27, \[x0, #-80\]
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.*: d9ffb81b stz2g x27, \[x0, #-80\]
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.*: d9e00c00 stz2g x0, \[x0, #0\]!
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.*: d9e00c00 stz2g x0, \[x0, #0\]!
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.*: d9e00c1f stz2g xzr, \[x0, #0\]!
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.*: d9e00c1f stz2g sp, \[x0, #0\]!
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.*: d9e0ac1b stz2g x27, \[x0, #160\]!
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.*: d9e0ac1b stz2g x27, \[x0, #160\]!
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.*: d9e00400 stz2g x0, \[x0\], #0
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.*: d9e00400 stz2g x0, \[x0\], #0
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.*: d9e0041f stz2g xzr, \[x0\], #0
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.*: d9e0041f stz2g sp, \[x0\], #0
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.*: d9fa641b stz2g x27, \[x0\], #-1440
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.*: d9fa641b stz2g x27, \[x0\], #-1440
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.*: d9effbe0 stz2g x0, \[sp, #4080\]
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.*: d9effbe0 stz2g x0, \[sp, #4080\]
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.*: d9effbff stz2g xzr, \[sp, #4080\]
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.*: d9effbff stz2g sp, \[sp, #4080\]
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.*: d9f00bfb stz2g x27, \[sp, #-4096\]
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.*: d9f00bfb stz2g x27, \[sp, #-4096\]
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.*: d9efffe0 stz2g x0, \[sp, #4080\]!
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.*: d9efffe0 stz2g x0, \[sp, #4080\]!
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.*: d9f007ff stz2g xzr, \[sp\], #-4096
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.*: d9f007ff stz2g sp, \[sp\], #-4096
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.*: 69000000 stgp x0, x0, \[x0\]
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.*: 69000000 stgp x0, x0, \[x0\]
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.*: 69006c00 stgp x0, x27, \[x0\]
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.*: 69006c00 stgp x0, x27, \[x0\]
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.*: 6900001b stgp x27, x0, \[x0\]
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.*: 6900001b stgp x27, x0, \[x0\]
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@ -19,19 +19,19 @@ func:
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.macro expand_stg op
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.macro expand_stg op
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\op x0, [x0, #0]
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\op x0, [x0, #0]
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\op x0, [x27, #0]
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\op x0, [x27, #0]
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\op xzr, [x0, #0]
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\op sp, [x0, #0]
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\op x27, [x0, #-80]
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\op x27, [x0, #-80]
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\op x0, [x0, #0]!
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\op x0, [x0, #0]!
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\op xzr, [x0, #0]!
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\op sp, [x0, #0]!
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\op x27, [x0, #160]!
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\op x27, [x0, #160]!
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\op x0, [x0], #0
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\op x0, [x0], #0
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\op xzr, [x0], #0
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\op sp, [x0], #0
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\op x27, [x0], #-1440
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\op x27, [x0], #-1440
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\op x0, [sp, #4080]
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\op x0, [sp, #4080]
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\op xzr, [sp, #4080]
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\op sp, [sp, #4080]
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\op x27, [sp, #-4096]
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\op x27, [sp, #-4096]
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\op x0, [sp, #4080]!
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\op x0, [sp, #4080]!
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\op xzr, [sp], #-4096
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\op sp, [sp], #-4096
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.endm
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.endm
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.macro expand_ldg_bulk op
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.macro expand_ldg_bulk op
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@ -38,10 +38,10 @@
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `st2g x2,\[xzr,#0\]!'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `st2g x2,\[xzr,#0\]!'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stzg x2,\[xzr\],#0'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stzg x2,\[xzr\],#0'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stz2g x2,\[xzr,#0\]'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stz2g x2,\[xzr,#0\]'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stg sp,\[x2,#0\]'
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[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stg xzr,\[x2,#0\]'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `st2g sp,\[x2,#0\]!'
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[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `st2g xzr,\[x2,#0\]!'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stzg sp,\[x2\],#0'
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[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stzg xzr,\[x2\],#0'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stz2g sp,\[x2,#0\]'
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[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stz2g xzr,\[x2,#0\]'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]'
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[^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]'
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[^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
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@ -51,10 +51,10 @@ func:
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st2g x2, [xzr, #0]!
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st2g x2, [xzr, #0]!
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stzg x2, [xzr], #0
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stzg x2, [xzr], #0
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stz2g x2, [xzr, #0]
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stz2g x2, [xzr, #0]
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stg sp, [x2, #0]
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stg xzr, [x2, #0]
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st2g sp, [x2, #0]!
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st2g xzr, [x2, #0]!
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stzg sp, [x2], #0
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stzg xzr, [x2], #0
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stz2g sp, [x2, #0]
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stz2g xzr, [x2, #0]
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stgp sp, x2, [x3]
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stgp sp, x2, [x3]
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stgp x1, sp, [x3]
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stgp x1, sp, [x3]
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stgp x0, x0, [xzr]
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stgp x0, x0, [xzr]
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@ -1,3 +1,7 @@
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2019-04-11 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
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2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
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2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
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* elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
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* elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
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@ -184,6 +184,7 @@ enum aarch64_opnd
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AARCH64_OPND_Rm, /* Integer register as source. */
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AARCH64_OPND_Rm, /* Integer register as source. */
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AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
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AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
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AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
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AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
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AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */
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AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
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AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
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AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
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AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
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AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
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AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
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@ -1,3 +1,16 @@
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|
2019-04-11 Sudakshina Das <sudi.das@arm.com>
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||||||
|
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* aarch64-opc.c (aarch64_print_operand): Add case for
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AARCH64_OPND_Rt_SP.
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(verify_constraints): Likewise.
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||||||
|
* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
|
||||||
|
(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
|
||||||
|
to accept Rt|SP as first operand.
|
||||||
|
(AARCH64_OPERANDS): Add new Rt_SP.
|
||||||
|
* aarch64-asm-2.c: Regenerated.
|
||||||
|
* aarch64-dis-2.c: Regenerated.
|
||||||
|
* aarch64-opc-2.c: Regenerated.
|
||||||
|
|
||||||
2019-04-11 Sudakshina Das <sudi.das@arm.com>
|
2019-04-11 Sudakshina Das <sudi.das@arm.com>
|
||||||
|
|
||||||
* aarch64-asm-2.c: Regenerated.
|
* aarch64-asm-2.c: Regenerated.
|
||||||
|
@ -613,11 +613,11 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||||||
case 9:
|
case 9:
|
||||||
case 10:
|
case 10:
|
||||||
case 11:
|
case 11:
|
||||||
case 15:
|
case 12:
|
||||||
case 16:
|
case 16:
|
||||||
case 17:
|
case 17:
|
||||||
case 18:
|
case 18:
|
||||||
case 20:
|
case 19:
|
||||||
case 21:
|
case 21:
|
||||||
case 22:
|
case 22:
|
||||||
case 23:
|
case 23:
|
||||||
@ -627,7 +627,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||||||
case 27:
|
case 27:
|
||||||
case 28:
|
case 28:
|
||||||
case 29:
|
case 29:
|
||||||
case 159:
|
case 30:
|
||||||
case 160:
|
case 160:
|
||||||
case 161:
|
case 161:
|
||||||
case 162:
|
case 162:
|
||||||
@ -637,7 +637,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||||||
case 166:
|
case 166:
|
||||||
case 167:
|
case 167:
|
||||||
case 168:
|
case 168:
|
||||||
case 181:
|
case 169:
|
||||||
case 182:
|
case 182:
|
||||||
case 183:
|
case 183:
|
||||||
case 184:
|
case 184:
|
||||||
@ -646,34 +646,34 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||||||
case 187:
|
case 187:
|
||||||
case 188:
|
case 188:
|
||||||
case 189:
|
case 189:
|
||||||
case 193:
|
case 190:
|
||||||
case 196:
|
case 194:
|
||||||
|
case 197:
|
||||||
return aarch64_ins_regno (self, info, code, inst, errors);
|
return aarch64_ins_regno (self, info, code, inst, errors);
|
||||||
case 13:
|
|
||||||
return aarch64_ins_reg_extended (self, info, code, inst, errors);
|
|
||||||
case 14:
|
case 14:
|
||||||
|
return aarch64_ins_reg_extended (self, info, code, inst, errors);
|
||||||
|
case 15:
|
||||||
return aarch64_ins_reg_shifted (self, info, code, inst, errors);
|
return aarch64_ins_reg_shifted (self, info, code, inst, errors);
|
||||||
case 19:
|
case 20:
|
||||||
return aarch64_ins_ft (self, info, code, inst, errors);
|
return aarch64_ins_ft (self, info, code, inst, errors);
|
||||||
case 30:
|
|
||||||
case 31:
|
case 31:
|
||||||
case 32:
|
case 32:
|
||||||
case 33:
|
case 33:
|
||||||
case 198:
|
|
||||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
|
||||||
case 34:
|
case 34:
|
||||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
case 199:
|
||||||
|
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||||
case 35:
|
case 35:
|
||||||
return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
|
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||||
case 36:
|
case 36:
|
||||||
return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
|
return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
|
||||||
case 37:
|
case 37:
|
||||||
return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
|
return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
|
||||||
case 38:
|
case 38:
|
||||||
|
return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
|
||||||
case 39:
|
case 39:
|
||||||
case 40:
|
case 40:
|
||||||
case 41:
|
case 41:
|
||||||
case 51:
|
case 42:
|
||||||
case 52:
|
case 52:
|
||||||
case 53:
|
case 53:
|
||||||
case 54:
|
case 54:
|
||||||
@ -689,13 +689,13 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||||||
case 64:
|
case 64:
|
||||||
case 65:
|
case 65:
|
||||||
case 66:
|
case 66:
|
||||||
case 78:
|
case 67:
|
||||||
case 79:
|
case 79:
|
||||||
case 80:
|
case 80:
|
||||||
case 81:
|
case 81:
|
||||||
case 156:
|
case 82:
|
||||||
case 158:
|
case 157:
|
||||||
case 173:
|
case 159:
|
||||||
case 174:
|
case 174:
|
||||||
case 175:
|
case 175:
|
||||||
case 176:
|
case 176:
|
||||||
@ -703,90 +703,90 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||||||
case 178:
|
case 178:
|
||||||
case 179:
|
case 179:
|
||||||
case 180:
|
case 180:
|
||||||
|
case 181:
|
||||||
return aarch64_ins_imm (self, info, code, inst, errors);
|
return aarch64_ins_imm (self, info, code, inst, errors);
|
||||||
case 42:
|
|
||||||
case 43:
|
case 43:
|
||||||
return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
|
|
||||||
case 44:
|
case 44:
|
||||||
|
return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
|
||||||
case 45:
|
case 45:
|
||||||
case 46:
|
case 46:
|
||||||
|
case 47:
|
||||||
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
|
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
|
||||||
case 50:
|
case 51:
|
||||||
case 147:
|
case 148:
|
||||||
return aarch64_ins_fpimm (self, info, code, inst, errors);
|
return aarch64_ins_fpimm (self, info, code, inst, errors);
|
||||||
case 67:
|
|
||||||
case 154:
|
|
||||||
return aarch64_ins_limm (self, info, code, inst, errors);
|
|
||||||
case 68:
|
case 68:
|
||||||
return aarch64_ins_aimm (self, info, code, inst, errors);
|
case 155:
|
||||||
|
return aarch64_ins_limm (self, info, code, inst, errors);
|
||||||
case 69:
|
case 69:
|
||||||
return aarch64_ins_imm_half (self, info, code, inst, errors);
|
return aarch64_ins_aimm (self, info, code, inst, errors);
|
||||||
case 70:
|
case 70:
|
||||||
|
return aarch64_ins_imm_half (self, info, code, inst, errors);
|
||||||
|
case 71:
|
||||||
return aarch64_ins_fbits (self, info, code, inst, errors);
|
return aarch64_ins_fbits (self, info, code, inst, errors);
|
||||||
case 72:
|
|
||||||
case 73:
|
case 73:
|
||||||
case 152:
|
|
||||||
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
|
|
||||||
case 74:
|
case 74:
|
||||||
case 151:
|
case 153:
|
||||||
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
|
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
|
||||||
case 75:
|
case 75:
|
||||||
|
case 152:
|
||||||
|
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
|
||||||
case 76:
|
case 76:
|
||||||
|
case 77:
|
||||||
return aarch64_ins_cond (self, info, code, inst, errors);
|
return aarch64_ins_cond (self, info, code, inst, errors);
|
||||||
case 82:
|
|
||||||
case 91:
|
|
||||||
return aarch64_ins_addr_simple (self, info, code, inst, errors);
|
|
||||||
case 83:
|
case 83:
|
||||||
return aarch64_ins_addr_regoff (self, info, code, inst, errors);
|
case 92:
|
||||||
|
return aarch64_ins_addr_simple (self, info, code, inst, errors);
|
||||||
case 84:
|
case 84:
|
||||||
|
return aarch64_ins_addr_regoff (self, info, code, inst, errors);
|
||||||
case 85:
|
case 85:
|
||||||
case 86:
|
case 86:
|
||||||
case 88:
|
|
||||||
case 90:
|
|
||||||
return aarch64_ins_addr_simm (self, info, code, inst, errors);
|
|
||||||
case 87:
|
case 87:
|
||||||
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
|
|
||||||
case 89:
|
case 89:
|
||||||
|
case 91:
|
||||||
|
return aarch64_ins_addr_simm (self, info, code, inst, errors);
|
||||||
|
case 88:
|
||||||
|
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
|
||||||
|
case 90:
|
||||||
return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
|
return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
|
||||||
case 92:
|
|
||||||
return aarch64_ins_addr_offset (self, info, code, inst, errors);
|
|
||||||
case 93:
|
case 93:
|
||||||
return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
|
return aarch64_ins_addr_offset (self, info, code, inst, errors);
|
||||||
case 94:
|
case 94:
|
||||||
return aarch64_ins_sysreg (self, info, code, inst, errors);
|
return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
|
||||||
case 95:
|
case 95:
|
||||||
return aarch64_ins_pstatefield (self, info, code, inst, errors);
|
return aarch64_ins_sysreg (self, info, code, inst, errors);
|
||||||
case 96:
|
case 96:
|
||||||
|
return aarch64_ins_pstatefield (self, info, code, inst, errors);
|
||||||
case 97:
|
case 97:
|
||||||
case 98:
|
case 98:
|
||||||
case 99:
|
case 99:
|
||||||
case 100:
|
case 100:
|
||||||
return aarch64_ins_sysins_op (self, info, code, inst, errors);
|
|
||||||
case 101:
|
case 101:
|
||||||
|
return aarch64_ins_sysins_op (self, info, code, inst, errors);
|
||||||
case 102:
|
case 102:
|
||||||
return aarch64_ins_barrier (self, info, code, inst, errors);
|
|
||||||
case 103:
|
case 103:
|
||||||
return aarch64_ins_prfop (self, info, code, inst, errors);
|
return aarch64_ins_barrier (self, info, code, inst, errors);
|
||||||
case 104:
|
case 104:
|
||||||
|
return aarch64_ins_prfop (self, info, code, inst, errors);
|
||||||
case 105:
|
case 105:
|
||||||
return aarch64_ins_hint (self, info, code, inst, errors);
|
|
||||||
case 106:
|
case 106:
|
||||||
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
|
return aarch64_ins_hint (self, info, code, inst, errors);
|
||||||
case 107:
|
case 107:
|
||||||
|
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
|
||||||
case 108:
|
case 108:
|
||||||
case 109:
|
case 109:
|
||||||
case 110:
|
case 110:
|
||||||
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
|
|
||||||
case 111:
|
case 111:
|
||||||
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
|
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
|
||||||
case 112:
|
case 112:
|
||||||
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
|
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
|
||||||
case 113:
|
case 113:
|
||||||
|
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
|
||||||
case 114:
|
case 114:
|
||||||
case 115:
|
case 115:
|
||||||
case 116:
|
case 116:
|
||||||
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
|
|
||||||
case 117:
|
case 117:
|
||||||
|
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
|
||||||
case 118:
|
case 118:
|
||||||
case 119:
|
case 119:
|
||||||
case 120:
|
case 120:
|
||||||
@ -799,8 +799,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||||||
case 127:
|
case 127:
|
||||||
case 128:
|
case 128:
|
||||||
case 129:
|
case 129:
|
||||||
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
|
|
||||||
case 130:
|
case 130:
|
||||||
|
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
|
||||||
case 131:
|
case 131:
|
||||||
case 132:
|
case 132:
|
||||||
case 133:
|
case 133:
|
||||||
@ -808,48 +808,49 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||||||
case 135:
|
case 135:
|
||||||
case 136:
|
case 136:
|
||||||
case 137:
|
case 137:
|
||||||
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
|
|
||||||
case 138:
|
case 138:
|
||||||
|
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
|
||||||
case 139:
|
case 139:
|
||||||
case 140:
|
case 140:
|
||||||
case 141:
|
case 141:
|
||||||
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
|
|
||||||
case 142:
|
case 142:
|
||||||
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
|
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
|
||||||
case 143:
|
case 143:
|
||||||
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
|
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
|
||||||
case 144:
|
case 144:
|
||||||
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
|
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
|
||||||
case 145:
|
case 145:
|
||||||
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
|
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
|
||||||
case 146:
|
case 146:
|
||||||
|
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
|
||||||
|
case 147:
|
||||||
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
|
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
|
||||||
case 148:
|
|
||||||
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
|
|
||||||
case 149:
|
case 149:
|
||||||
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
|
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
|
||||||
case 150:
|
case 150:
|
||||||
|
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
|
||||||
|
case 151:
|
||||||
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
|
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
|
||||||
case 153:
|
case 154:
|
||||||
return aarch64_ins_inv_limm (self, info, code, inst, errors);
|
return aarch64_ins_inv_limm (self, info, code, inst, errors);
|
||||||
case 155:
|
case 156:
|
||||||
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
|
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
|
||||||
case 157:
|
case 158:
|
||||||
return aarch64_ins_sve_scale (self, info, code, inst, errors);
|
return aarch64_ins_sve_scale (self, info, code, inst, errors);
|
||||||
case 169:
|
|
||||||
case 170:
|
case 170:
|
||||||
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
|
|
||||||
case 171:
|
case 171:
|
||||||
|
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
|
||||||
case 172:
|
case 172:
|
||||||
|
case 173:
|
||||||
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
|
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
|
||||||
case 190:
|
|
||||||
case 191:
|
case 191:
|
||||||
case 192:
|
case 192:
|
||||||
|
case 193:
|
||||||
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
|
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
|
||||||
case 194:
|
|
||||||
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
|
||||||
case 195:
|
case 195:
|
||||||
case 197:
|
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
||||||
|
case 196:
|
||||||
|
case 198:
|
||||||
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
|
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
|
||||||
default: assert (0); abort ();
|
default: assert (0); abort ();
|
||||||
}
|
}
|
||||||
|
@ -20027,14 +20027,14 @@ aarch64_extract_operand (const aarch64_operand *self,
|
|||||||
case 5:
|
case 5:
|
||||||
case 6:
|
case 6:
|
||||||
case 7:
|
case 7:
|
||||||
case 9:
|
case 8:
|
||||||
case 10:
|
case 10:
|
||||||
case 11:
|
case 11:
|
||||||
case 15:
|
case 12:
|
||||||
case 16:
|
case 16:
|
||||||
case 17:
|
case 17:
|
||||||
case 18:
|
case 18:
|
||||||
case 20:
|
case 19:
|
||||||
case 21:
|
case 21:
|
||||||
case 22:
|
case 22:
|
||||||
case 23:
|
case 23:
|
||||||
@ -20044,7 +20044,7 @@ aarch64_extract_operand (const aarch64_operand *self,
|
|||||||
case 27:
|
case 27:
|
||||||
case 28:
|
case 28:
|
||||||
case 29:
|
case 29:
|
||||||
case 159:
|
case 30:
|
||||||
case 160:
|
case 160:
|
||||||
case 161:
|
case 161:
|
||||||
case 162:
|
case 162:
|
||||||
@ -20054,7 +20054,7 @@ aarch64_extract_operand (const aarch64_operand *self,
|
|||||||
case 166:
|
case 166:
|
||||||
case 167:
|
case 167:
|
||||||
case 168:
|
case 168:
|
||||||
case 181:
|
case 169:
|
||||||
case 182:
|
case 182:
|
||||||
case 183:
|
case 183:
|
||||||
case 184:
|
case 184:
|
||||||
@ -20063,38 +20063,38 @@ aarch64_extract_operand (const aarch64_operand *self,
|
|||||||
case 187:
|
case 187:
|
||||||
case 188:
|
case 188:
|
||||||
case 189:
|
case 189:
|
||||||
case 193:
|
case 190:
|
||||||
case 196:
|
case 194:
|
||||||
|
case 197:
|
||||||
return aarch64_ext_regno (self, info, code, inst, errors);
|
return aarch64_ext_regno (self, info, code, inst, errors);
|
||||||
case 8:
|
case 9:
|
||||||
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
|
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
|
||||||
case 12:
|
|
||||||
return aarch64_ext_regno_pair (self, info, code, inst, errors);
|
|
||||||
case 13:
|
case 13:
|
||||||
return aarch64_ext_reg_extended (self, info, code, inst, errors);
|
return aarch64_ext_regno_pair (self, info, code, inst, errors);
|
||||||
case 14:
|
case 14:
|
||||||
|
return aarch64_ext_reg_extended (self, info, code, inst, errors);
|
||||||
|
case 15:
|
||||||
return aarch64_ext_reg_shifted (self, info, code, inst, errors);
|
return aarch64_ext_reg_shifted (self, info, code, inst, errors);
|
||||||
case 19:
|
case 20:
|
||||||
return aarch64_ext_ft (self, info, code, inst, errors);
|
return aarch64_ext_ft (self, info, code, inst, errors);
|
||||||
case 30:
|
|
||||||
case 31:
|
case 31:
|
||||||
case 32:
|
case 32:
|
||||||
case 33:
|
case 33:
|
||||||
case 198:
|
|
||||||
return aarch64_ext_reglane (self, info, code, inst, errors);
|
|
||||||
case 34:
|
case 34:
|
||||||
return aarch64_ext_reglist (self, info, code, inst, errors);
|
case 199:
|
||||||
|
return aarch64_ext_reglane (self, info, code, inst, errors);
|
||||||
case 35:
|
case 35:
|
||||||
return aarch64_ext_ldst_reglist (self, info, code, inst, errors);
|
return aarch64_ext_reglist (self, info, code, inst, errors);
|
||||||
case 36:
|
case 36:
|
||||||
return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors);
|
return aarch64_ext_ldst_reglist (self, info, code, inst, errors);
|
||||||
case 37:
|
case 37:
|
||||||
return aarch64_ext_ldst_elemlist (self, info, code, inst, errors);
|
return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors);
|
||||||
case 38:
|
case 38:
|
||||||
|
return aarch64_ext_ldst_elemlist (self, info, code, inst, errors);
|
||||||
case 39:
|
case 39:
|
||||||
case 40:
|
case 40:
|
||||||
case 41:
|
case 41:
|
||||||
case 51:
|
case 42:
|
||||||
case 52:
|
case 52:
|
||||||
case 53:
|
case 53:
|
||||||
case 54:
|
case 54:
|
||||||
@ -20110,14 +20110,14 @@ aarch64_extract_operand (const aarch64_operand *self,
|
|||||||
case 64:
|
case 64:
|
||||||
case 65:
|
case 65:
|
||||||
case 66:
|
case 66:
|
||||||
case 77:
|
case 67:
|
||||||
case 78:
|
case 78:
|
||||||
case 79:
|
case 79:
|
||||||
case 80:
|
case 80:
|
||||||
case 81:
|
case 81:
|
||||||
case 156:
|
case 82:
|
||||||
case 158:
|
case 157:
|
||||||
case 173:
|
case 159:
|
||||||
case 174:
|
case 174:
|
||||||
case 175:
|
case 175:
|
||||||
case 176:
|
case 176:
|
||||||
@ -20125,92 +20125,92 @@ aarch64_extract_operand (const aarch64_operand *self,
|
|||||||
case 178:
|
case 178:
|
||||||
case 179:
|
case 179:
|
||||||
case 180:
|
case 180:
|
||||||
|
case 181:
|
||||||
return aarch64_ext_imm (self, info, code, inst, errors);
|
return aarch64_ext_imm (self, info, code, inst, errors);
|
||||||
case 42:
|
|
||||||
case 43:
|
case 43:
|
||||||
return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors);
|
|
||||||
case 44:
|
case 44:
|
||||||
|
return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors);
|
||||||
case 45:
|
case 45:
|
||||||
case 46:
|
case 46:
|
||||||
return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors);
|
|
||||||
case 47:
|
case 47:
|
||||||
|
return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors);
|
||||||
|
case 48:
|
||||||
return aarch64_ext_shll_imm (self, info, code, inst, errors);
|
return aarch64_ext_shll_imm (self, info, code, inst, errors);
|
||||||
case 50:
|
case 51:
|
||||||
case 147:
|
case 148:
|
||||||
return aarch64_ext_fpimm (self, info, code, inst, errors);
|
return aarch64_ext_fpimm (self, info, code, inst, errors);
|
||||||
case 67:
|
|
||||||
case 154:
|
|
||||||
return aarch64_ext_limm (self, info, code, inst, errors);
|
|
||||||
case 68:
|
case 68:
|
||||||
return aarch64_ext_aimm (self, info, code, inst, errors);
|
case 155:
|
||||||
|
return aarch64_ext_limm (self, info, code, inst, errors);
|
||||||
case 69:
|
case 69:
|
||||||
return aarch64_ext_imm_half (self, info, code, inst, errors);
|
return aarch64_ext_aimm (self, info, code, inst, errors);
|
||||||
case 70:
|
case 70:
|
||||||
|
return aarch64_ext_imm_half (self, info, code, inst, errors);
|
||||||
|
case 71:
|
||||||
return aarch64_ext_fbits (self, info, code, inst, errors);
|
return aarch64_ext_fbits (self, info, code, inst, errors);
|
||||||
case 72:
|
|
||||||
case 73:
|
case 73:
|
||||||
case 152:
|
|
||||||
return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
|
|
||||||
case 74:
|
case 74:
|
||||||
case 151:
|
case 153:
|
||||||
return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
|
return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
|
||||||
case 75:
|
case 75:
|
||||||
|
case 152:
|
||||||
|
return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
|
||||||
case 76:
|
case 76:
|
||||||
|
case 77:
|
||||||
return aarch64_ext_cond (self, info, code, inst, errors);
|
return aarch64_ext_cond (self, info, code, inst, errors);
|
||||||
case 82:
|
|
||||||
case 91:
|
|
||||||
return aarch64_ext_addr_simple (self, info, code, inst, errors);
|
|
||||||
case 83:
|
case 83:
|
||||||
return aarch64_ext_addr_regoff (self, info, code, inst, errors);
|
case 92:
|
||||||
|
return aarch64_ext_addr_simple (self, info, code, inst, errors);
|
||||||
case 84:
|
case 84:
|
||||||
|
return aarch64_ext_addr_regoff (self, info, code, inst, errors);
|
||||||
case 85:
|
case 85:
|
||||||
case 86:
|
case 86:
|
||||||
case 88:
|
|
||||||
case 90:
|
|
||||||
return aarch64_ext_addr_simm (self, info, code, inst, errors);
|
|
||||||
case 87:
|
case 87:
|
||||||
return aarch64_ext_addr_simm10 (self, info, code, inst, errors);
|
|
||||||
case 89:
|
case 89:
|
||||||
|
case 91:
|
||||||
|
return aarch64_ext_addr_simm (self, info, code, inst, errors);
|
||||||
|
case 88:
|
||||||
|
return aarch64_ext_addr_simm10 (self, info, code, inst, errors);
|
||||||
|
case 90:
|
||||||
return aarch64_ext_addr_uimm12 (self, info, code, inst, errors);
|
return aarch64_ext_addr_uimm12 (self, info, code, inst, errors);
|
||||||
case 92:
|
|
||||||
return aarch64_ext_addr_offset (self, info, code, inst, errors);
|
|
||||||
case 93:
|
case 93:
|
||||||
return aarch64_ext_simd_addr_post (self, info, code, inst, errors);
|
return aarch64_ext_addr_offset (self, info, code, inst, errors);
|
||||||
case 94:
|
case 94:
|
||||||
return aarch64_ext_sysreg (self, info, code, inst, errors);
|
return aarch64_ext_simd_addr_post (self, info, code, inst, errors);
|
||||||
case 95:
|
case 95:
|
||||||
return aarch64_ext_pstatefield (self, info, code, inst, errors);
|
return aarch64_ext_sysreg (self, info, code, inst, errors);
|
||||||
case 96:
|
case 96:
|
||||||
|
return aarch64_ext_pstatefield (self, info, code, inst, errors);
|
||||||
case 97:
|
case 97:
|
||||||
case 98:
|
case 98:
|
||||||
case 99:
|
case 99:
|
||||||
case 100:
|
case 100:
|
||||||
return aarch64_ext_sysins_op (self, info, code, inst, errors);
|
|
||||||
case 101:
|
case 101:
|
||||||
|
return aarch64_ext_sysins_op (self, info, code, inst, errors);
|
||||||
case 102:
|
case 102:
|
||||||
return aarch64_ext_barrier (self, info, code, inst, errors);
|
|
||||||
case 103:
|
case 103:
|
||||||
return aarch64_ext_prfop (self, info, code, inst, errors);
|
return aarch64_ext_barrier (self, info, code, inst, errors);
|
||||||
case 104:
|
case 104:
|
||||||
|
return aarch64_ext_prfop (self, info, code, inst, errors);
|
||||||
case 105:
|
case 105:
|
||||||
return aarch64_ext_hint (self, info, code, inst, errors);
|
|
||||||
case 106:
|
case 106:
|
||||||
return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors);
|
return aarch64_ext_hint (self, info, code, inst, errors);
|
||||||
case 107:
|
case 107:
|
||||||
|
return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors);
|
||||||
case 108:
|
case 108:
|
||||||
case 109:
|
case 109:
|
||||||
case 110:
|
case 110:
|
||||||
return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors);
|
|
||||||
case 111:
|
case 111:
|
||||||
return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors);
|
return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors);
|
||||||
case 112:
|
case 112:
|
||||||
return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors);
|
return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors);
|
||||||
case 113:
|
case 113:
|
||||||
|
return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors);
|
||||||
case 114:
|
case 114:
|
||||||
case 115:
|
case 115:
|
||||||
case 116:
|
case 116:
|
||||||
return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors);
|
|
||||||
case 117:
|
case 117:
|
||||||
|
return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors);
|
||||||
case 118:
|
case 118:
|
||||||
case 119:
|
case 119:
|
||||||
case 120:
|
case 120:
|
||||||
@ -20223,8 +20223,8 @@ aarch64_extract_operand (const aarch64_operand *self,
|
|||||||
case 127:
|
case 127:
|
||||||
case 128:
|
case 128:
|
||||||
case 129:
|
case 129:
|
||||||
return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
|
|
||||||
case 130:
|
case 130:
|
||||||
|
return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
|
||||||
case 131:
|
case 131:
|
||||||
case 132:
|
case 132:
|
||||||
case 133:
|
case 133:
|
||||||
@ -20232,48 +20232,49 @@ aarch64_extract_operand (const aarch64_operand *self,
|
|||||||
case 135:
|
case 135:
|
||||||
case 136:
|
case 136:
|
||||||
case 137:
|
case 137:
|
||||||
return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
|
|
||||||
case 138:
|
case 138:
|
||||||
|
return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
|
||||||
case 139:
|
case 139:
|
||||||
case 140:
|
case 140:
|
||||||
case 141:
|
case 141:
|
||||||
return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
|
|
||||||
case 142:
|
case 142:
|
||||||
return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
|
return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
|
||||||
case 143:
|
case 143:
|
||||||
return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
|
return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
|
||||||
case 144:
|
case 144:
|
||||||
return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
|
return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
|
||||||
case 145:
|
case 145:
|
||||||
return aarch64_ext_sve_aimm (self, info, code, inst, errors);
|
return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
|
||||||
case 146:
|
case 146:
|
||||||
|
return aarch64_ext_sve_aimm (self, info, code, inst, errors);
|
||||||
|
case 147:
|
||||||
return aarch64_ext_sve_asimm (self, info, code, inst, errors);
|
return aarch64_ext_sve_asimm (self, info, code, inst, errors);
|
||||||
case 148:
|
|
||||||
return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
|
|
||||||
case 149:
|
case 149:
|
||||||
return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
|
return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
|
||||||
case 150:
|
case 150:
|
||||||
|
return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
|
||||||
|
case 151:
|
||||||
return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors);
|
return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors);
|
||||||
case 153:
|
case 154:
|
||||||
return aarch64_ext_inv_limm (self, info, code, inst, errors);
|
return aarch64_ext_inv_limm (self, info, code, inst, errors);
|
||||||
case 155:
|
case 156:
|
||||||
return aarch64_ext_sve_limm_mov (self, info, code, inst, errors);
|
return aarch64_ext_sve_limm_mov (self, info, code, inst, errors);
|
||||||
case 157:
|
case 158:
|
||||||
return aarch64_ext_sve_scale (self, info, code, inst, errors);
|
return aarch64_ext_sve_scale (self, info, code, inst, errors);
|
||||||
case 169:
|
|
||||||
case 170:
|
case 170:
|
||||||
return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
|
|
||||||
case 171:
|
case 171:
|
||||||
|
return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
|
||||||
case 172:
|
case 172:
|
||||||
|
case 173:
|
||||||
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
|
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
|
||||||
case 190:
|
|
||||||
case 191:
|
case 191:
|
||||||
case 192:
|
case 192:
|
||||||
|
case 193:
|
||||||
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
|
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
|
||||||
case 194:
|
|
||||||
return aarch64_ext_sve_index (self, info, code, inst, errors);
|
|
||||||
case 195:
|
case 195:
|
||||||
case 197:
|
return aarch64_ext_sve_index (self, info, code, inst, errors);
|
||||||
|
case 196:
|
||||||
|
case 198:
|
||||||
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
|
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
|
||||||
default: assert (0); abort ();
|
default: assert (0); abort ();
|
||||||
}
|
}
|
||||||
|
@ -30,6 +30,7 @@ const struct aarch64_operand aarch64_operands[] =
|
|||||||
{AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"},
|
{AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"},
|
||||||
{AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
|
{AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
|
||||||
{AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register"},
|
{AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register"},
|
||||||
|
{AARCH64_OPND_CLASS_INT_REG, "Rt_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer or stack pointer register"},
|
||||||
{AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register"},
|
{AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register"},
|
||||||
{AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register"},
|
{AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register"},
|
||||||
{AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
|
{AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
|
||||||
|
@ -3156,6 +3156,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
|||||||
|
|
||||||
case AARCH64_OPND_Rd_SP:
|
case AARCH64_OPND_Rd_SP:
|
||||||
case AARCH64_OPND_Rn_SP:
|
case AARCH64_OPND_Rn_SP:
|
||||||
|
case AARCH64_OPND_Rt_SP:
|
||||||
case AARCH64_OPND_SVE_Rn_SP:
|
case AARCH64_OPND_SVE_Rn_SP:
|
||||||
case AARCH64_OPND_Rm_SP:
|
case AARCH64_OPND_Rm_SP:
|
||||||
assert (opnd->qualifier == AARCH64_OPND_QLF_W
|
assert (opnd->qualifier == AARCH64_OPND_QLF_W
|
||||||
@ -4928,6 +4929,7 @@ verify_constraints (const struct aarch64_inst *inst,
|
|||||||
case AARCH64_OPND_Rn:
|
case AARCH64_OPND_Rn:
|
||||||
case AARCH64_OPND_Rm:
|
case AARCH64_OPND_Rm:
|
||||||
case AARCH64_OPND_Rn_SP:
|
case AARCH64_OPND_Rn_SP:
|
||||||
|
case AARCH64_OPND_Rt_SP:
|
||||||
case AARCH64_OPND_Rm_SP:
|
case AARCH64_OPND_Rm_SP:
|
||||||
if (inst_op.reg.regno == blk_dest.reg.regno)
|
if (inst_op.reg.regno == blk_dest.reg.regno)
|
||||||
{
|
{
|
||||||
|
@ -125,10 +125,11 @@
|
|||||||
QLF1(X), \
|
QLF1(X), \
|
||||||
}
|
}
|
||||||
|
|
||||||
/* e.g. STG Xt, [<Xn|SP>, #<imm9>]. */
|
/* e.g. STG <Xt|SP>, [<Xn|SP>, #<imm9>]. */
|
||||||
#define QL_LDST_AT \
|
#define QL_LDST_AT \
|
||||||
{ \
|
{ \
|
||||||
QLF2(X, imm_tag), \
|
QLF2(X, imm_tag), \
|
||||||
|
QLF2(SP, imm_tag), \
|
||||||
}
|
}
|
||||||
|
|
||||||
/* e.g. RBIT <Wd>, <Wn>. */
|
/* e.g. RBIT <Wd>, <Wn>. */
|
||||||
@ -3239,14 +3240,14 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||||||
CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
|
CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
|
||||||
CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
|
CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
|
||||||
/* Load/store Allocation Tag instructions. */
|
/* Load/store Allocation Tag instructions. */
|
||||||
MEMTAG_INSN ("stg", 0xd9200800, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
|
MEMTAG_INSN ("stg", 0xd9200800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
|
||||||
MEMTAG_INSN ("stzg", 0xd9600800, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
|
MEMTAG_INSN ("stzg", 0xd9600800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
|
||||||
MEMTAG_INSN ("st2g", 0xd9a00800, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
|
MEMTAG_INSN ("st2g", 0xd9a00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
|
||||||
MEMTAG_INSN ("stz2g",0xd9e00800, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
|
MEMTAG_INSN ("stz2g",0xd9e00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
|
||||||
MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
|
MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
|
||||||
MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
|
MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
|
||||||
MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
|
MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
|
||||||
MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
|
MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
|
||||||
/* Load/store register (unsigned immediate). */
|
/* Load/store register (unsigned immediate). */
|
||||||
CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
|
CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
|
||||||
CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
|
CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
|
||||||
@ -4520,6 +4521,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||||||
Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \
|
Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \
|
||||||
Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \
|
Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \
|
||||||
Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \
|
Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \
|
||||||
|
Y(INT_REG, regno, "Rt_SP", OPD_F_MAYBE_SP, F(FLD_Rt), \
|
||||||
|
"an integer or stack pointer register") \
|
||||||
Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register") \
|
Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register") \
|
||||||
Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \
|
Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \
|
||||||
X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt), \
|
X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt), \
|
||||||
|
Reference in New Issue
Block a user