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* config/tc-bfin.c (md_assemble): Bump line counters if there is

Browse Source 
EOL in the instruction.

	testsuite/
	* gas/bfin/line_number.l, gas/bfin/line_number.s: New test.
	* gas/bfin/bfin.exp: Add the new test.
This commit is contained in:
Jie Zhang
2009-09-03 16:32:42 +00:00
parent c958a8a8fb
commit bd03da3089
6 changed files with 22 additions and 0 deletions
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5
gas/ChangeLog
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@ -1,3 +1,8 @@
2009-09-03 Jie Zhang <jie.zhang@analog.com>
* config/tc-bfin.c (md_assemble): Bump line counters if there is
EOL in the instruction.
2009-09-03 Jie Zhang <jie.zhang@analog.com> 2009-09-03 Jie Zhang <jie.zhang@analog.com>
* config/bfin-defs.h (IS_GENREG): Define. * config/bfin-defs.h (IS_GENREG): Define.

4
gas/config/tc-bfin.c
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@ -712,6 +712,10 @@ md_assemble (char *line)
#ifdef OBJ_ELF #ifdef OBJ_ELF
dwarf2_emit_insn (insn_size); dwarf2_emit_insn (insn_size);
#endif #endif
while (*line++ != '\0')
if (*line == '\n')
bump_line_counters ();
} }
/* Parse one line of instructions, and generate opcode for it. /* Parse one line of instructions, and generate opcode for it.

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gas/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2009-09-03 Jie Zhang <jie.zhang@analog.com>
* gas/bfin/line_number.l, gas/bfin/line_number.s: New test.
* gas/bfin/bfin.exp: Add the new test.
2009-09-03 Jie Zhang <jie.zhang@analog.com> 2009-09-03 Jie Zhang <jie.zhang@analog.com>
* gas/bfin/expected_move_errors.s, * gas/bfin/expected_move_errors.s,

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gas/testsuite/gas/bfin/bfin.exp
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@ -17,6 +17,7 @@ if [istarget bfin*-*-*] {
run_dump_test "flow" run_dump_test "flow"
run_dump_test "flow2" run_dump_test "flow2"
run_list_test "invalid_arith_mode" "" run_list_test "invalid_arith_mode" ""
run_list_test "line_number" ""
run_dump_test "load" run_dump_test "load"
run_dump_test "logical" run_dump_test "logical"
run_dump_test "logical2" run_dump_test "logical2"

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gas/testsuite/gas/bfin/line_number.l Normal file
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@ -0,0 +1,3 @@
.*: Assembler messages:
.*:4: Error: syntax error. Input text was illegal.
.*:4: Error:

4
gas/testsuite/gas/bfin/line_number.s Normal file
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@ -0,0 +1,4 @@
R1 = ROT R0 BY 0 ||
R3 = [SP+12] ||
nop;
ILLEGAL;