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PowerPC: Add support for RFC02658 - MMA+ Outer-Product Instructions
gas/ * config/tc-ppc.c (md_assemble): Only check for prefix opcodes. * testsuite/gas/ppc/rfc02658.s: New test. * testsuite/gas/ppc/rfc02658.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. opcodes/ * ppc-opc.c (XMSK8, P_GERX4_MASK, P_GERX2_MASK, XX3GERX_MASK): New. (powerpc_opcodes): Add dmxvi8gerx4pp, dmxvi8gerx4, dmxvf16gerx2pp, dmxvf16gerx2, dmxvbf16gerx2pp, dmxvf16gerx2np, dmxvbf16gerx2, dmxvi8gerx4spp, dmxvbf16gerx2np, dmxvf16gerx2pn, dmxvbf16gerx2pn, dmxvf16gerx2nn, dmxvbf16gerx2nn, pmdmxvi8gerx4pp, pmdmxvi8gerx4, pmdmxvf16gerx2pp, pmdmxvf16gerx2, pmdmxvbf16gerx2pp, pmdmxvf16gerx2np, pmdmxvbf16gerx2, pmdmxvi8gerx4spp, pmdmxvbf16gerx2np, pmdmxvf16gerx2pn, pmdmxvbf16gerx2pn, pmdmxvf16gerx2nn, pmdmxvbf16gerx2nn.
This commit is contained in:
Peter Bergner
@ -4065,8 +4065,7 @@ md_assemble (char *str)
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insn_length = 4;
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if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && PPC_OP_SE_VLE (insn))
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insn_length = 2;
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else if ((opcode->flags & PPC_OPCODE_POWER10) != 0
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&& PPC_PREFIX_P (insn))
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else if (PPC_PREFIX_P (insn))
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{
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struct insn_label_list *l;
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@ -146,6 +146,7 @@ run_dump_test "scalarquad"
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run_dump_test "rop"
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run_dump_test "rop-checks"
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run_dump_test "rfc02653"
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run_dump_test "rfc02658"
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run_dump_test "dcbt"
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run_dump_test "pr27676"
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51
gas/testsuite/gas/ppc/rfc02658.d
Normal file
51
gas/testsuite/gas/ppc/rfc02658.d
Normal file
@ -0,0 +1,51 @@
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#as: -mfuture
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#objdump: -dr -Mfuture
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#name: RFC02658 tests
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.*
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Disassembly of section \.text:
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0+0 <_start>:
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.*: (d8 12 00 ec|ec 00 12 d8) dmxvbf16gerx2 dm0,vs0,vs2
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.*: (50 67 8a ec|ec 8a 67 50) dmxvbf16gerx2nn dm1,vs10,vs12
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.*: (98 b3 14 ed|ed 14 b3 98) dmxvbf16gerx2np dm2,vs20,vs22
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.*: (9a 05 9e ed|ed 9e 05 9a) dmxvbf16gerx2pn dm3,vs30,vs32
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.*: (56 52 08 ee|ee 08 52 56) dmxvbf16gerx2pp dm4,vs40,vs42
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.*: (1e a2 92 ee|ee 92 a2 1e) dmxvf16gerx2 dm5,vs50,vs52
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.*: (56 f6 1c ef|ef 1c f6 56) dmxvf16gerx2nn dm6,vs60,vs62
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.*: (98 72 8c ef|ef 8c 72 98) dmxvf16gerx2np dm7,vs12,vs14
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.*: (98 84 0e ec|ec 0e 84 98) dmxvf16gerx2pn dm0,vs14,vs16
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.*: (10 92 90 ec|ec 90 92 10) dmxvf16gerx2pp dm1,vs16,vs18
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.*: (58 a0 12 ed|ed 12 a0 58) dmxvi8gerx4 dm2,vs18,vs20
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.*: (50 c0 96 ed|ed 96 c0 50) dmxvi8gerx4pp dm3,vs22,vs24
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.*: (10 d3 18 ee|ee 18 d3 10) dmxvi8gerx4spp dm4,vs24,vs26
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.*: (ff cf 90 07|07 90 cf ff) pmdmxvbf16gerx2nn dm0,vs0,vs2,255,15,3
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.*: (50 17 00 ec|ec 00 17 50)
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (ff cf 90 07|07 90 cf ff) pmdmxvbf16gerx2np dm1,vs10,vs12,255,15,3
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.*: (98 63 8a ec|ec 8a 63 98)
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.*: (ff cf 90 07|07 90 cf ff) pmdmxvbf16gerx2 dm2,vs20,vs22,255,15,3
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.*: (d8 b2 14 ed|ed 14 b2 d8)
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.*: (ff cf 90 07|07 90 cf ff) pmdmxvbf16gerx2pn dm3,vs30,vs32,255,15,3
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.*: (9a 05 9e ed|ed 9e 05 9a)
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.*: (ff cf 90 07|07 90 cf ff) pmdmxvbf16gerx2pp dm4,vs40,vs42,255,15,3
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.*: (56 52 08 ee|ee 08 52 56)
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.*: (ff cf 90 07|07 90 cf ff) pmdmxvf16gerx2nn dm5,vs50,vs52,255,15,3
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.*: (56 a6 92 ee|ee 92 a6 56)
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.*: (ff cf 90 07|07 90 cf ff) pmdmxvf16gerx2np dm6,vs60,vs62,255,15,3
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.*: (9e f2 1c ef|ef 1c f2 9e)
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.*: (ff cf 90 07|07 90 cf ff) pmdmxvf16gerx2 dm7,vs12,vs14,255,15,3
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.*: (18 72 8c ef|ef 8c 72 18)
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.*: (ff cf 90 07|07 90 cf ff) pmdmxvf16gerx2pn dm0,vs14,vs16,255,15,3
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.*: (98 84 0e ec|ec 0e 84 98)
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.*: (ff cf 90 07|07 90 cf ff) pmdmxvf16gerx2pp dm1,vs16,vs18,255,15,3
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.*: (10 92 90 ec|ec 90 92 10)
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.*: (ff ff 90 07|07 90 ff ff) pmdmxvi8gerx4 dm2,vs18,vs20,255,15,15
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.*: (58 a0 12 ed|ed 12 a0 58)
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.*: (ff ff 90 07|07 90 ff ff) pmdmxvi8gerx4pp dm3,vs22,vs24,255,15,15
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.*: (50 c0 96 ed|ed 96 c0 50)
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.*: (ff ff 90 07|07 90 ff ff) pmdmxvi8gerx4spp dm4,vs24,vs26,255,15,15
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.*: (10 d3 18 ee|ee 18 d3 10)
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#pass
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28
gas/testsuite/gas/ppc/rfc02658.s
Normal file
28
gas/testsuite/gas/ppc/rfc02658.s
Normal file
@ -0,0 +1,28 @@
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.text
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_start:
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dmxvbf16gerx2 0,0,2
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dmxvbf16gerx2nn 1,10,12
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dmxvbf16gerx2np 2,20,22
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dmxvbf16gerx2pn 3,30,32
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dmxvbf16gerx2pp 4,40,42
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dmxvf16gerx2 5,50,52
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dmxvf16gerx2nn 6,60,62
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dmxvf16gerx2np 7,12,14
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dmxvf16gerx2pn 0,14,16
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dmxvf16gerx2pp 1,16,18
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dmxvi8gerx4 2,18,20
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dmxvi8gerx4pp 3,22,24
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dmxvi8gerx4spp 4,24,26
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pmdmxvbf16gerx2nn 0,0,2,0xff,0xf,0x3
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pmdmxvbf16gerx2np 1,10,12,0xff,0xf,0x3
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pmdmxvbf16gerx2 2,20,22,0xff,0xf,0x3
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pmdmxvbf16gerx2pn 3,30,32,0xff,0xf,0x3
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pmdmxvbf16gerx2pp 4,40,42,0xff,0xf,0x3
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pmdmxvf16gerx2nn 5,50,52,0xff,0xf,0x3
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pmdmxvf16gerx2np 6,60,62,0xff,0xf,0x3
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pmdmxvf16gerx2 7,12,14,0xff,0xf,0x3
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pmdmxvf16gerx2pn 0,14,16,0xff,0xf,0x3
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pmdmxvf16gerx2pp 1,16,18,0xff,0xf,0x3
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pmdmxvi8gerx4 2,18,20,0xff,0xf,0xf
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pmdmxvi8gerx4pp 3,22,24,0xff,0xf,0xf
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pmdmxvi8gerx4spp 4,24,26,0xff,0xf,0xf
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@ -3083,8 +3083,12 @@ const struct powerpc_operand powerpc_operands[] =
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#define XMSK PMSK2 + 1
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{ 0xf, 36, NULL, NULL, 0 },
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/* The XMSK field in GERX prefix instructions. */
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#define XMSK8 XMSK + 1
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{ 0xff, 36, NULL, NULL, 0 },
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/* The YMSK field in GER prefix instructions. */
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#define YMSK XMSK + 1
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#define YMSK XMSK8 + 1
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{ 0xf, 32, NULL, NULL, 0 },
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/* The YMSK field in 64-bit GER prefix instructions. */
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@ -4014,6 +4018,8 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
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#define P_GER4_MASK (P_GER_MASK & ~(15ULL << 44))
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#define P_GER8_MASK (P_GER_MASK & ~(255ULL << 40))
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#define P_GER64_MASK (P_GER_MASK | (3ULL << 32))
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#define P_GERX4_MASK ((-1ULL << 48) | XX3GERX_MASK)
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#define P_GERX2_MASK (P_GERX4_MASK & ~(3ULL << 46))
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/* Vector splat immediate op. */
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#define VSOP(op, xop) (OP (op) | (xop << 17))
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@ -4554,6 +4560,7 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
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#define XX3ACC_MASK (XX3_MASK | (3 << 21) | 1)
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#define XX3DMR_MASK (XX3ACC_MASK | (1 << 11))
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#define XX2DMR_MASK (XX2ACC_MASK | (0xf << 17))
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#define XX3GERX_MASK (XX3ACC_MASK | (1 << 16))
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/* The mask for an XX4 form instruction. */
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#define XX4_MASK XX4 (0x3f, 0x3)
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@ -9036,6 +9043,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
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{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
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{"dmxvi8gerx4pp", XX3(59,10), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
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{"dmxvi8gerx4", XX3(59,11), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
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{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
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{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
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@ -9092,24 +9102,31 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
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{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
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{"dmxvf16gerx2pp", XX3(59,66), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
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{"dmxvf16gerx2", XX3(59,67), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
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{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
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{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
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{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
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{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
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{"dmxvbf16gerx2pp", XX3(59,74), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
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{"dmxvi16ger2", XX3(59,75), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"xvi16ger2", XX3(59,75), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"dmxvf16ger2np", XX3(59,82), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"xvf16ger2np", XX3(59,82), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"dmxvf16gerx2np",XX3(59,83), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
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{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
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{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
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{"dmxvf32gernp", XX3(59,90), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"xvf32gernp", XX3(59,90), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"dmxvbf16gerx2", XX3(59,91), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
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{"dmxvi8gerx4spp",XX3(59,98), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
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{"dmxvi8ger4spp", XX3(59,99), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"xvi8ger4spp", XX3(59,99), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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@ -9118,6 +9135,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"dmxvbf16ger2np",XX3(59,114), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"xvbf16ger2np", XX3(59,114), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"dmxvbf16gerx2np",XX3(59,115), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
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{"dmxvf64gernp", XX3(59,122), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
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{"xvf64gernp", XX3(59,122), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
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@ -9130,6 +9148,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"dmxvf16ger2pn", XX3(59,146), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"xvf16ger2pn", XX3(59,146), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"dmxvf16gerx2pn",XX3(59,147), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
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{"dmxvf32gerpn",XX3(59,154), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"xvf32gerpn", XX3(59,154), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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@ -9141,6 +9160,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"dmxvbf16ger2pn",XX3(59,178), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"xvbf16ger2pn", XX3(59,178), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"dmxvbf16gerx2pn", XX3(59,179),XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
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{"dmxvf64gerpn",XX3(59,186), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
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{"xvf64gerpn", XX3(59,186), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
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@ -9151,6 +9171,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
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{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
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{"dmxvf16gerx2nn", XX3(59,202), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
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{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
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{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
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@ -9166,6 +9188,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"dmxvf32gernn",XX3(59,218), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"xvf32gernn", XX3(59,218), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"dmxvbf16gerx2nn", XX3(59,234),XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
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{"dmxvbf16ger2nn",XX3(59,242), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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{"xvbf16ger2nn", XX3(59,242), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
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@ -9761,6 +9785,8 @@ const struct powerpc_opcode prefix_opcodes[] = {
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{"pmxvi8ger4pp", PMMIRR|XX3(59,2), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
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{"pmdmxvi8ger4", PMMIRR|XX3(59,3), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
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{"pmxvi8ger4", PMMIRR|XX3(59,3), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
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{"pmdmxvi8gerx4pp",PMMIRR|XX3(59,10), P_GERX4_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK4}},
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{"pmdmxvi8gerx4", PMMIRR|XX3(59,11), P_GERX4_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK4}},
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{"pmdmxvf16ger2pp",PMMIRR|XX3(59,18), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
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{"pmxvf16ger2pp", PMMIRR|XX3(59,18), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
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{"pmdmxvf16ger2", PMMIRR|XX3(59,19), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
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@ -9785,32 +9811,43 @@ const struct powerpc_opcode prefix_opcodes[] = {
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{"pmxvf64gerpp", PMMIRR|XX3(59,58), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
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{"pmdmxvf64ger", PMMIRR|XX3(59,59), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
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{"pmxvf64ger", PMMIRR|XX3(59,59), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
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{"pmdmxvf16gerx2pp",PMMIRR|XX3(59,66), P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
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{"pmdmxvf16gerx2",PMMIRR|XX3(59,67), P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
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{"pmdmxvbf16gerx2pp",PMMIRR|XX3(59,74),P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
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{"pmdmxvi16ger2", PMMIRR|XX3(59,75), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
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{"pmxvi16ger2", PMMIRR|XX3(59,75), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
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{"pmdmxvf16ger2np",PMMIRR|XX3(59,82), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
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{"pmxvf16ger2np", PMMIRR|XX3(59,82), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
||||
{"pmdmxvf16gerx2np",PMMIRR|XX3(59,83), P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
|
||||
{"pmdmxvf32gernp",PMMIRR|XX3(59,90), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
|
||||
{"pmxvf32gernp", PMMIRR|XX3(59,90), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
|
||||
{"pmdmxvbf16gerx2",PMMIRR|XX3(59,91), P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
|
||||
{"pmdmxvi8gerx4spp",PMMIRR|XX3(59,98), P_GERX4_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK4}},
|
||||
{"pmdmxvi8ger4spp",PMMIRR|XX3(59,99), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
|
||||
{"pmxvi8ger4spp", PMMIRR|XX3(59,99), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
|
||||
{"pmdmxvi16ger2pp",PMMIRR|XX3(59,107), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
||||
{"pmxvi16ger2pp", PMMIRR|XX3(59,107), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
||||
{"pmdmxvbf16ger2np",PMMIRR|XX3(59,114),P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
||||
{"pmxvbf16ger2np",PMMIRR|XX3(59,114), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
||||
{"pmdmxvbf16gerx2np",PMMIRR|XX3(59,115),P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
|
||||
{"pmdmxvf64gernp",PMMIRR|XX3(59,122), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
|
||||
{"pmxvf64gernp", PMMIRR|XX3(59,122), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
|
||||
{"pmdmxvf16ger2pn",PMMIRR|XX3(59,146), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
||||
{"pmxvf16ger2pn", PMMIRR|XX3(59,146), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
||||
{"pmdmxvf16gerx2pn",PMMIRR|XX3(59,147),P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
|
||||
{"pmdmxvf32gerpn",PMMIRR|XX3(59,154), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
|
||||
{"pmxvf32gerpn", PMMIRR|XX3(59,154), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
|
||||
{"pmdmxvbf16ger2pn",PMMIRR|XX3(59,178),P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
||||
{"pmxvbf16ger2pn",PMMIRR|XX3(59,178), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
||||
{"pmdmxvbf16gerx2pn",PMMIRR|XX3(59,179),P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
|
||||
{"pmdmxvf64gerpn",PMMIRR|XX3(59,186), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
|
||||
{"pmxvf64gerpn", PMMIRR|XX3(59,186), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
|
||||
{"pmdmxvf16gerx2nn",PMMIRR|XX3(59,202),P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
|
||||
{"pmdmxvf16ger2nn",PMMIRR|XX3(59,210), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
||||
{"pmxvf16ger2nn", PMMIRR|XX3(59,210), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
||||
{"pmdmxvf32gernn",PMMIRR|XX3(59,218), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
|
||||
{"pmxvf32gernn", PMMIRR|XX3(59,218), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
|
||||
{"pmdmxvbf16gerx2nn",PMMIRR|XX3(59,234),P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
|
||||
{"pmdmxvbf16ger2nn",PMMIRR|XX3(59,242),P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
||||
{"pmxvbf16ger2nn",PMMIRR|XX3(59,242), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
|
||||
{"pmdmxvf64gernn",PMMIRR|XX3(59,250), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
|
||||
|
||||
Reference in New Issue
Block a user