mirror of
https://github.com/espressif/binutils-gdb.git
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include/opcode/
* mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
Update comment before MIPS16 field descriptors to mention MIPS16.
(OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
BBIT.
(OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
New bit masks and shift counts for cins and exts.
gas/
* config/tc-mips.c (validate_mips_insn): Handle field descriptors
+x, +X, +p, +P, +s, +S.
(mips_ip): Likewise.
opcodes/
* mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
+s, +S.
* mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
syncw, syncws, vm3mulu, vm0 and vmulu.
gas/testsuite/
* gas/mips/octeon.s, gas/mips/octeon.d: Add tests for baddu,
bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, syncw,
syncws, vm3mulu, vm0 and vmulu.
* gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: New test.
* gas/mips/mips.exp: Run it. Run octeon test with
run_dump_test_arches.
This commit is contained in:
Nick Clifton
@ -1,3 +1,9 @@
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2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
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* config/tc-mips.c (validate_mips_insn): Handle field descriptors
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+x, +X, +p, +P, +s, +S.
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(mips_ip): Likewise.
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2008-06-09 Eric B. Weddington <eric.weddington@atmel.com>
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* config/tc-avr.c (mcu_types): Remove support for ATmega32HVB device.
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@ -8268,6 +8268,13 @@ validate_mips_insn (const struct mips_opcode *opc)
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case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
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case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
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USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
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case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
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case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
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case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
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case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
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case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
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case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
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default:
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as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
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c, opc->name, opc->args);
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@ -8967,6 +8974,100 @@ do_msbd:
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as_bad (_("Invalid coprocessor 0 register number"));
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break;
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case 'x':
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/* bbit[01] and bbit[01]32 bit index. Give error if index
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is not in the valid range. */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((unsigned) imm_expr.X_add_number > 31)
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{
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as_bad (_("Improper bit index (%lu)"),
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(unsigned long) imm_expr.X_add_number);
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imm_expr.X_add_number = 0;
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}
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INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
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imm_expr.X_op = O_absent;
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s = expr_end;
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continue;
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case 'X':
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/* bbit[01] bit index when bbit is used but we generate
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bbit[01]32 because the index is over 32. Move to the
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next candidate if index is not in the valid range. */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((unsigned) imm_expr.X_add_number < 32
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|| (unsigned) imm_expr.X_add_number > 63)
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break;
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INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
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imm_expr.X_op = O_absent;
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s = expr_end;
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continue;
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case 'p':
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/* cins, cins32, exts and exts32 position field. Give error
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if it's not in the valid range. */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((unsigned) imm_expr.X_add_number > 31)
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{
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as_bad (_("Improper position (%lu)"),
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(unsigned long) imm_expr.X_add_number);
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imm_expr.X_add_number = 0;
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}
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/* Make the pos explicit to simplify +S. */
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lastpos = imm_expr.X_add_number + 32;
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INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
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imm_expr.X_op = O_absent;
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s = expr_end;
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continue;
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case 'P':
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/* cins, cins32, exts and exts32 position field. Move to
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the next candidate if it's not in the valid range. */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((unsigned) imm_expr.X_add_number < 32
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|| (unsigned) imm_expr.X_add_number > 63)
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break;
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lastpos = imm_expr.X_add_number;
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INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
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imm_expr.X_op = O_absent;
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s = expr_end;
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continue;
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case 's':
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/* cins and exts length-minus-one field. */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((unsigned long) imm_expr.X_add_number > 31)
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{
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as_bad (_("Improper size (%lu)"),
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(unsigned long) imm_expr.X_add_number);
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imm_expr.X_add_number = 0;
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}
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INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
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imm_expr.X_op = O_absent;
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s = expr_end;
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continue;
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case 'S':
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/* cins32/exts32 and cins/exts aliasing cint32/exts32
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length-minus-one field. */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((long) imm_expr.X_add_number < 0
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|| (unsigned long) imm_expr.X_add_number + lastpos > 63)
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{
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as_bad (_("Improper size (%lu)"),
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(unsigned long) imm_expr.X_add_number);
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imm_expr.X_add_number = 0;
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}
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INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
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imm_expr.X_op = O_absent;
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s = expr_end;
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continue;
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default:
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as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
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*args, insn->name, insn->args);
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@ -1,3 +1,12 @@
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2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
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* gas/mips/octeon.s, gas/mips/octeon.d: Add tests for baddu,
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bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, syncw,
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syncws, vm3mulu, vm0 and vmulu.
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* gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: New test.
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* gas/mips/mips.exp: Run it. Run octeon test with
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run_dump_test_arches.
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2008-06-03 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Run sse-check-none and
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@ -776,7 +776,9 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test "loongson-2e"
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run_dump_test "loongson-2f"
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run_dump_test "octeon"
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run_dump_test_arches "octeon" [mips_arch_list_matching octeon]
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run_list_test_arches "octeon-ill" "" \
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[mips_arch_list_matching octeon]
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run_dump_test "smartmips"
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run_dump_test "mips32-dsp"
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15
gas/testsuite/gas/mips/octeon-ill.l
Normal file
15
gas/testsuite/gas/mips/octeon-ill.l
Normal file
@ -0,0 +1,15 @@
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.*: Assembler messages:
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.*:5: Error: Improper bit index \(51\)
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.*:7: Error: Improper bit index \(71\)
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.*:10: Error: Improper bit index \(49\)
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.*:12: Error: Improper bit index \(74\)
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.*:15: Error: Improper size \(37\)
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.*:17: Error: Improper position \(39\)
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.*:18: Error: Improper size \(25\)
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.*:20: Error: Improper position \(64\)
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.*:21: Error: Improper size \(14\)
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.*:23: Error: Improper size \(32\)
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.*:25: Error: Improper position \(32\)
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.*:26: Error: Improper size \(29\)
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.*:28: Error: Improper position \(70\)
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.*:29: Error: Improper size \(25\)
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29
gas/testsuite/gas/mips/octeon-ill.s
Normal file
29
gas/testsuite/gas/mips/octeon-ill.s
Normal file
@ -0,0 +1,29 @@
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.text
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.set noreorder
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foo:
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bbit032 $23,51,foo
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nop
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bbit0 $23,71,foo
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nop
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bbit132 $23,49,foo
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nop
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bbit1 $23,74,foo
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nop
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cins $2,0,37
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cins32 $19,$31,39,12
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cins32 $17,$20,7,25
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cins $24,$10,64,8
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cins $21,$30,50,14
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exts $26,26,32
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exts32 $7,$21,32,10
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exts32 $31,$13,3,29
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exts $14,$29,70,14
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exts $20,$16,39,25
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@ -6,6 +6,53 @@
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Disassembly of section .text:
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[0-9a-f]+ <sync_insns>:
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[0-9a-f]+ <foo>:
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.*: 72538828 baddu \$17,\$18,\$19
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.*: 70431028 baddu \$2,\$2,\$3
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.*: ca76fffd bbit0 \$19,0x16,[0-9a-f]+ <foo>
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.*: 00000000 nop
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.*: dbcbfffb bbit032 \$30,0xb,[0-9a-f]+ <foo>
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.*: 00000000 nop
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.*: d90afff9 bbit032 \$8,0xa,[0-9a-f]+ <foo>
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.*: 00000000 nop
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.*: e87ffff7 bbit1 \$3,0x1f,[0-9a-f]+ <foo>
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.*: 00000000 nop
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.*: fb0afff5 bbit132 \$24,0xa,[0-9a-f]+ <foo>
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.*: 00000000 nop
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.*: f9cefff3 bbit132 \$14,0xe,[0-9a-f]+ <foo>
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.*: 00000000 nop
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.*: 715915b2 cins \$25,\$10,0x16,0x2
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.*: 7129ec72 cins \$9,\$9,0x11,0x1d
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.*: 704f44b3 cins32 \$15,\$2,0x12,0x8
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.*: 72d6b273 cins32 \$22,\$22,0x9,0x16
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.*: 73f8f833 cins32 \$24,\$31,0x0,0x1f
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.*: 71ef2973 cins32 \$15,\$15,0x5,0x5
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.*: 731c9803 dmul \$19,\$24,\$28
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.*: 72b9a803 dmul \$21,\$21,\$25
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.*: 7260402c pop \$8,\$19
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.*: 7040102c pop \$2,\$2
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.*: 72c0782d dpop \$15,\$22
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.*: 7180602d dpop \$12,\$12
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.*: 73847efa exts \$4,\$28,0x1b,0xf
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.*: 71ef347a exts \$15,\$15,0x11,0x6
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.*: 71a442bb exts32 \$4,\$13,0xa,0x8
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.*: 71efa2fb exts32 \$15,\$15,0xb,0x14
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.*: 70874dbb exts32 \$7,\$4,0x16,0x9
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.*: 7339c97b exts32 \$25,\$25,0x5,0x19
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.*: 73400008 mtm0 \$26
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.*: 7260000c mtm1 \$19
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.*: 7240000d mtm2 \$18
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.*: 72000009 mtp0 \$16
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.*: 7320000a mtp1 \$25
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.*: 7120000b mtp2 \$9
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.*: 0000008f synciobdma
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.*: 0000018f syncs
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.*: 0000010f syncw
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.*: 0000014f syncws
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.*: 7155a811 v3mulu \$21,\$10,\$21
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.*: 728aa011 v3mulu \$20,\$20,\$10
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.*: 72701810 vmm0 \$3,\$19,\$16
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.*: 73e9f810 vmm0 \$31,\$31,\$9
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.*: 7151e80f vmulu \$29,\$10,\$17
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.*: 7366d80f vmulu \$27,\$27,\$6
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#pass
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@ -1,6 +1,62 @@
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.text
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.set noreorder
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sync_insns:
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synciobdma
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foo:
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baddu $17,$18,$19
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baddu $2,$3
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|
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bbit0 $19,22,foo
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nop
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||||
bbit032 $30,11,foo
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nop
|
||||
bbit0 $8,42,foo
|
||||
nop
|
||||
|
||||
bbit1 $3,31,foo
|
||||
nop
|
||||
bbit132 $24,10,foo
|
||||
nop
|
||||
bbit1 $14,46,foo
|
||||
nop
|
||||
|
||||
cins $25,$10,22,2
|
||||
cins $9,17,29
|
||||
cins32 $15,$2,18,8
|
||||
cins32 $22,9,22
|
||||
cins $24,$31,32,31
|
||||
cins $15,37,5
|
||||
|
||||
dmul $19,$24,$28
|
||||
dmul $21,$25
|
||||
|
||||
pop $8,$19
|
||||
pop $2
|
||||
dpop $15,$22
|
||||
dpop $12
|
||||
|
||||
exts $4,$28,27,15
|
||||
exts $15,17,6
|
||||
exts32 $4,$13,10,8
|
||||
exts32 $15,11,20
|
||||
exts $7,$4,54,9
|
||||
exts $25,37,25
|
||||
|
||||
mtm0 $26
|
||||
mtm1 $19
|
||||
mtm2 $18
|
||||
|
||||
mtp0 $16
|
||||
mtp1 $25
|
||||
mtp2 $9
|
||||
|
||||
synciobdma
|
||||
syncs
|
||||
syncw
|
||||
syncws
|
||||
|
||||
v3mulu $21,$10,$21
|
||||
v3mulu $20,$10
|
||||
vmm0 $3,$19,$16
|
||||
vmm0 $31,$9
|
||||
vmulu $29,$10,$17
|
||||
vmulu $27,$6
|
||||
|
||||
@ -1,3 +1,12 @@
|
||||
2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
|
||||
|
||||
* mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
|
||||
Update comment before MIPS16 field descriptors to mention MIPS16.
|
||||
(OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
|
||||
BBIT.
|
||||
(OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
|
||||
New bit masks and shift counts for cins and exts.
|
||||
|
||||
2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
|
||||
|
||||
* mips.h (INSN_MACRO): Move it up to the the pinfo macros.
|
||||
|
||||
@ -215,6 +215,14 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
|
||||
#define OP_SH_UDI4 6
|
||||
#define OP_MASK_UDI4 0xfffff
|
||||
|
||||
/* Octeon */
|
||||
#define OP_SH_BBITIND 16
|
||||
#define OP_MASK_BBITIND 0x1f
|
||||
#define OP_SH_CINSPOS 6
|
||||
#define OP_MASK_CINSPOS 0x1f
|
||||
#define OP_SH_CINSLM1 11
|
||||
#define OP_MASK_CINSLM1 0x1f
|
||||
|
||||
/* This structure holds information for a particular instruction. */
|
||||
|
||||
struct mips_opcode
|
||||
@ -370,6 +378,19 @@ struct mips_opcode
|
||||
"+3" UDI immediate bits 6-20
|
||||
"+4" UDI immediate bits 6-25
|
||||
|
||||
Octeon:
|
||||
"+x" Bit index field of bbit. Enforces: 0 <= index < 32.
|
||||
"+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64,
|
||||
otherwise skips to next candidate.
|
||||
"+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
|
||||
"+P" Position field of cins/exts aliasing cins32/exts32. Matches if
|
||||
32 <= pos < 64, otherwise skips to next candidate.
|
||||
"+s" Length-minus-one field of cins/exts. Enforces: 0 <= lenm1 < 32.
|
||||
"+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
|
||||
cint32/exts32. Enforces non-negative value and that
|
||||
pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
|
||||
position field is "+p" or "+P".
|
||||
|
||||
Other:
|
||||
"()" parens surrounding optional value
|
||||
"," separates operands
|
||||
@ -385,8 +406,8 @@ struct mips_opcode
|
||||
Extension character sequences used so far ("+" followed by the
|
||||
following), for quick reference when adding more:
|
||||
"1234"
|
||||
"ABCDEFGHIT"
|
||||
"t"
|
||||
"ABCDEFGHIPSTX"
|
||||
"pstx"
|
||||
*/
|
||||
|
||||
/* These are the bits which may be set in the pinfo field of an
|
||||
@ -962,11 +983,10 @@ extern int bfd_mips_num_opcodes;
|
||||
#define MIPS16OP_MASK_IMM6 0x3f
|
||||
#define MIPS16OP_SH_IMM6 5
|
||||
|
||||
/* These are the characters which may appears in the args field of an
|
||||
instruction. They appear in the order in which the fields appear
|
||||
when the instruction is used. Commas and parentheses in the args
|
||||
string are ignored when assembling, and written into the output
|
||||
when disassembling.
|
||||
/* These are the characters which may appears in the args field of a MIPS16
|
||||
instruction. They appear in the order in which the fields appear when the
|
||||
instruction is used. Commas and parentheses in the args string are ignored
|
||||
when assembling, and written into the output when disassembling.
|
||||
|
||||
"y" 3 bit register (MIPS16OP_*_RY)
|
||||
"x" 3 bit register (MIPS16OP_*_RX)
|
||||
|
||||
@ -1,3 +1,11 @@
|
||||
2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
|
||||
|
||||
* mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
|
||||
+s, +S.
|
||||
* mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
|
||||
baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
|
||||
syncw, syncws, vm3mulu, vm0 and vmulu.
|
||||
|
||||
2008-05-30 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-opc.tbl: Add vmovd with 64bit operand.
|
||||
|
||||
@ -882,6 +882,26 @@ print_insn_args (const char *d,
|
||||
break;
|
||||
}
|
||||
|
||||
case 'x': /* bbit bit index */
|
||||
(*info->fprintf_func) (info->stream, "0x%lx",
|
||||
(l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
|
||||
break;
|
||||
|
||||
case 'p': /* cins, cins32, exts and exts32 position */
|
||||
(*info->fprintf_func) (info->stream, "0x%lx",
|
||||
(l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
|
||||
break;
|
||||
|
||||
case 's': /* cins and exts length-minus-one */
|
||||
(*info->fprintf_func) (info->stream, "0x%lx",
|
||||
(l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
|
||||
break;
|
||||
|
||||
case 'S': /* cins32 and exts32 length-minus-one field */
|
||||
(*info->fprintf_func) (info->stream, "0x%lx",
|
||||
(l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* xgettext:c-format */
|
||||
(*info->fprintf_func) (info->stream,
|
||||
|
||||
@ -244,8 +244,15 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
|
||||
{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
|
||||
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
|
||||
{"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
|
||||
/* b is at the top of the table. */
|
||||
/* bal is at the top of the table. */
|
||||
{"bbit032", "s,+x,p", 0xd8000000, 0xfc000000, RD_s|CBD, 0, IOCT },
|
||||
{"bbit0", "s,+X,p", 0xd8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, /* bbit032 */
|
||||
{"bbit0", "s,+x,p", 0xc8000000, 0xfc000000, RD_s|CBD, 0, IOCT },
|
||||
{"bbit132", "s,+x,p", 0xf8000000, 0xfc000000, RD_s|CBD, 0, IOCT },
|
||||
{"bbit1", "s,+X,p", 0xf8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, /* bbit132 */
|
||||
{"bbit1", "s,+x,p", 0xe8000000, 0xfc000000, RD_s|CBD, 0, IOCT },
|
||||
/* bc0[tf]l? are at the bottom of the table. */
|
||||
{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
|
||||
{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
|
||||
@ -514,6 +521,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
|
||||
{"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
|
||||
{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
|
||||
{"cins32", "t,r,+p,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT },
|
||||
{"cins", "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* cins32 */
|
||||
{"cins", "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s, 0, IOCT },
|
||||
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
|
||||
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
|
||||
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
|
||||
@ -619,6 +629,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
/* dmtc2 is at the bottom of the table. */
|
||||
/* dmfc3 is at the bottom of the table. */
|
||||
/* dmtc3 is at the bottom of the table. */
|
||||
{"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, IOCT },
|
||||
{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 },
|
||||
{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 },
|
||||
{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 },
|
||||
@ -629,6 +640,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
|
||||
{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */
|
||||
{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/
|
||||
{"dpop", "d,v", 0x7000002d, 0xfc1f07ff, WR_d|RD_s, 0, IOCT },
|
||||
{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
|
||||
{"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3 },
|
||||
{"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3 },
|
||||
@ -688,6 +700,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
|
||||
{"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
|
||||
{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
|
||||
{"exts32", "t,r,+p,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT },
|
||||
{"exts", "t,r,+P,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* exts32 */
|
||||
{"exts", "t,r,+p,+s",0x7000003a, 0xfc00003f, WR_t|RD_s, 0, IOCT },
|
||||
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 },
|
||||
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
|
||||
{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
|
||||
@ -940,6 +955,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
|
||||
{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 },
|
||||
{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT },
|
||||
{"mtm0", "s", 0x70000008, 0xfc1fffff, RD_s, 0, IOCT },
|
||||
{"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_s, 0, IOCT },
|
||||
{"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_s, 0, IOCT },
|
||||
{"mtp0", "s", 0x70000009, 0xfc1fffff, RD_s, 0, IOCT },
|
||||
{"mtp1", "s", 0x7000000a, 0xfc1fffff, RD_s, 0, IOCT },
|
||||
{"mtp2", "s", 0x7000000b, 0xfc1fffff, RD_s, 0, IOCT },
|
||||
{"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
|
||||
{"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
|
||||
{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
|
||||
@ -1070,6 +1091,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
|
||||
{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 },
|
||||
{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 },
|
||||
{"pop", "d,v", 0x7000002c, 0xfc1f07ff, WR_d|RD_s, 0, IOCT },
|
||||
/* pref and prefx are at the start of the table. */
|
||||
{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 },
|
||||
{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 },
|
||||
@ -1297,6 +1319,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 },
|
||||
{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 },
|
||||
{"synciobdma", "", 0x0000008f, 0xffffffff, INSN_SYNC, 0, IOCT },
|
||||
{"syncs", "", 0x0000018f, 0xffffffff, INSN_SYNC, 0, IOCT },
|
||||
{"syncw", "", 0x0000010f, 0xffffffff, INSN_SYNC, 0, IOCT },
|
||||
{"syncws", "", 0x0000014f, 0xffffffff, INSN_SYNC, 0, IOCT },
|
||||
{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 },
|
||||
{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 },
|
||||
{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
|
||||
@ -1355,6 +1380,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
|
||||
{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
|
||||
{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
|
||||
{"v3mulu", "d,v,t", 0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
|
||||
{"vmm0", "d,v,t", 0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
|
||||
{"vmulu", "d,v,t", 0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
|
||||
{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 },
|
||||
{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 },
|
||||
{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX },
|
||||
|
||||
Reference in New Issue
Block a user