mirror of
https://github.com/espressif/binutils-gdb.git
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checkpoint vr5400 additions
This commit is contained in:
Ken Raeburn
@ -156,6 +156,34 @@ else
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done
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fi
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vr5400_files="ChangeLog mips.h"
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if ( echo $* | grep keep\-vr5400 > /dev/null ) ; then
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for i in $vr5400_files ; do
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if test ! -d $i && (grep sanitize-vr5400 $i > /dev/null) ; then
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if [ -n "${verbose}" ] ; then
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echo Keeping vr5400 stuff in $i
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fi
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fi
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done
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else
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for i in $vr5400_files ; do
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if test ! -d $i && (grep sanitize-vr5400 $i > /dev/null) ; then
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if [ -n "${verbose}" ] ; then
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echo Removing traces of \"vr5400\" from $i...
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fi
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cp $i new
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sed '/start\-sanitize\-vr5400/,/end-\sanitize\-vr5400/d' < $i > new
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if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
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if [ -n "${verbose}" ] ; then
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echo Caching $i in .Recover...
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fi
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mv $i .Recover
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fi
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mv new $i
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fi
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done
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fi
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tic80_files="ChangeLog"
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if ( echo $* | grep keep\-tic80 > /dev/null ) ; then
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for i in $tic80_files ; do
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@ -1,3 +1,12 @@
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Fri Oct 24 22:36:20 1997 Ken Raeburn <raeburn@cygnus.com>
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* mips.h: Added to comments a quick-ref list of all assigned
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operand type characters.
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start-sanitize-vr5400
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(OP_{MASK,SH}_{PERFREG,VECBYTE,VECALIGN}): New macros for VR5400
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support.
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end-sanitize-vr5400
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Wed Oct 22 17:28:33 1997 Richard Henderson <rth@cygnus.com>
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* sparc.h: Add '_' and '/' for v9a asr's.
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@ -1,5 +1,5 @@
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/* mips.h. Mips opcode list for GDB, the GNU debugger.
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Copyright 1993, 94, 95, 1996 Free Software Foundation, Inc.
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Copyright 1993, 94, 95, 96, 1997 Free Software Foundation, Inc.
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Contributed by Ralph Campbell and OSF
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Commented and modified by Ian Lance Taylor, Cygnus Support
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@ -121,6 +121,15 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define OP_MASK_MMI 0x3f
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#define OP_SH_MMISUB 6
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#define OP_MASK_MMISUB 0x1f
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/* start-sanitize-vr5400 */
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#define OP_MASK_PERFREG 0x1f /* Performance monitoring */
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#define OP_SH_PERFREG 1
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#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
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but 0x8-0xf don't select bytes. */
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#define OP_SH_VECBYTE 22
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#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
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#define OP_SH_VECALIGN 21
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/* end-sanitize-vr5400 */
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/* This structure holds information for a particular instruction. */
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@ -146,6 +155,9 @@ struct mips_opcode
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of bits describing the instruction, notably any relevant hazard
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information. */
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unsigned long pinfo;
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/* A collection of bits describing the instruction sets of which this
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instruction is a member. */
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unsigned long membership;
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};
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/* These are the characters which may appears in the args field of an
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@ -166,6 +178,9 @@ struct mips_opcode
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"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
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"j" 16 bit signed immediate (OP_*_DELTA)
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"k" 5 bit cache opcode in target register position (OP_*_CACHE)
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start-sanitize-vr5400
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also vr5400 vector ops immediate operand
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end-sanitize-vr5400
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"o" 16 bit signed offset (OP_*_DELTA)
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"p" 16 bit PC relative branch target address (OP_*_DELTA)
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"r" 5 bit same register used as both source and target (OP_*_RS)
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@ -192,6 +207,12 @@ struct mips_opcode
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Coprocessor instructions:
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"E" 5 bit target register (OP_*_RT)
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"G" 5 bit destination register (OP_*_RD)
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start-sanitize-vr5400
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"P" 5 bit performance-monitor register (OP_*_PERFREG)
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"e" 5 bit vector register byte specifier (OP_*_VECBYTE)
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"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
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see also "k" above
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end-sanitize-vr5400
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Macro instructions:
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"A" General 32 bit expression
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@ -200,6 +221,14 @@ struct mips_opcode
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"L" 64 bit floating point constant in .lit8
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"f" 32 bit floating point constant
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"l" 32 bit floating point constant in .lit4
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Characters used so far, for quick reference when adding more:
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start-sanitize-vr5400
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"Pe%" plus...
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end-sanitize-vr5400
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"<>"
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"ABCDEFGILMNSTRVW"
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"abcdfhijkloprstuvwxz"
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*/
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/* These are the bits which may be set in the pinfo field of an
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@ -261,29 +290,53 @@ struct mips_opcode
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#define INSN_TRAP 0x04000000
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/* Instruction stores value into memory. */
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#define INSN_STORE_MEMORY 0x08000000
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/* MIPS ISA field--CPU level at which insn is supported. */
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#define INSN_ISA 0x70000000
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/* MIPS ISA 2 instruction (R6000 or R4000). */
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#define INSN_ISA2 0x10000000
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/* MIPS ISA 3 instruction (R4000). */
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#define INSN_ISA3 0x20000000
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/* MIPS R4650 instruction. */
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#define INSN_4650 0x30000000
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/* MIPS ISA 4 instruction (R8000). */
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#define INSN_ISA4 0x40000000
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/* LSI R4010 instruction. */
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#define INSN_4010 0x50000000
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/* NEC VR4100 instruction. */
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#define INSN_4100 0x60000000
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/* start-sanitize-r5900 */
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/* Toshiba R5900 instruction */
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#define INSN_5900 0x70000000
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/* end-sanitize-r5900 */
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/* Instruction uses single precision floating point. */
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#define FP_S 0x10000000
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/* Instruction uses double precision floating point. */
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#define FP_D 0x20000000
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/* As yet unused bits: 0x40000000 */
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/* Instruction is actually a macro. It should be ignored by the
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disassembler, and requires special treatment by the assembler. */
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#define INSN_MACRO 0xffffffff
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/* MIPS ISA field--CPU level at which insn is supported. */
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#define INSN_ISA 0x0000000F
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/* An instruction which is not part of any basic MIPS ISA.
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(ie it is a chip specific instruction) */
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#define INSN_NO_ISA 0x00000000
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/* MIPS ISA 1 instruction. */
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#define INSN_ISA1 0x00000001
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/* MIPS ISA 2 instruction (R6000 or R4000). */
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#define INSN_ISA2 0x00000002
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/* MIPS ISA 3 instruction (R4000). */
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#define INSN_ISA3 0x00000003
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/* MIPS ISA 4 instruction (R8000). */
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#define INSN_ISA4 0x00000004
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/* Chip specific instructions. These are bitmasks. */
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/* MIPS R4650 instruction. */
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#define INSN_4650 0x00000010
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/* LSI R4010 instruction. */
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#define INSN_4010 0x00000020
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/* NEC VR4100 instruction. */
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#define INSN_4100 0x00000040
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/* Toshiba R3900 instruction. */
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#define INSN_3900 0x00000080
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/* start-sanitize-vr5400 */
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/* NEC VR5400 instruction. */
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#define INSN_5400 0x00001000
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/* end-sanitize-vr5400 */
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/* start-sanitize-r5900 */
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/* Toshiba R5900 instruction */
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#define INSN_5900 0x00000100
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/* end-sanitize-r5900 */
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/* This is a list of macro expanded instructions.
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*
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* _I appended means immediate
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