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sim: d10v: fix signal updates

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Way back in aba6488e0b73756f31f154d12a228baa82a68d8a, a bunch of signal
defines were changed to TARGET_SIGNAL_xxx.  For d10v, the transition was
incomplete which lead to sim_stop_reason using the new set but sim_resume
still using the old set.  Which meant in some cases, the sim would never
actually stop.

Convert all the remaining SIGxxx defines in here to TARGET_SIGNAL_xxx.
This has the nice side effect of fixing the testsuite.
This commit is contained in:
Mike Frysinger
2015-04-02 20:15:43 -04:00
parent ef6f73553e
commit b366059a5b
2 changed files with 11 additions and 8 deletions
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6
sim/d10v/ChangeLog
View File

@ -1,3 +1,9 @@
2015-04-02 Mike Frysinger <vapier@gentoo.org>
* interp.c (lookup_hash): Change SIGILL to GDB_SIGNAL_ILL.
(sim_resume): Change SIGBUS/SIGSEGV to GDB_SIGNAL_BUS, SIGILL to
GDB_SIGNAL_ILL, and SIGTRAP to GDB_SIGNAL_TRAP.
2015-04-01 Mike Frysinger <vapier@gentoo.org> 2015-04-01 Mike Frysinger <vapier@gentoo.org>
* interp.c (sim_set_profile, sim_set_profile_size): Delete. * interp.c (sim_set_profile, sim_set_profile_size): Delete.

13
sim/d10v/interp.c
View File

@ -80,7 +80,7 @@ lookup_hash (uint32 ins, int size)
{ {
if (h->next == NULL) if (h->next == NULL)
{ {
State.exception = SIGILL; State.exception = GDB_SIGNAL_ILL;
State.pc_changed = 1; /* Don't increment the PC. */ State.pc_changed = 1; /* Don't increment the PC. */
return NULL; return NULL;
} }
@ -936,17 +936,14 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
{ {
case 0: case 0:
break; break;
#ifdef SIGBUS case GDB_SIGNAL_BUS:
case SIGBUS:
#endif
case SIGSEGV:
SET_BPC (PC); SET_BPC (PC);
SET_BPSW (PSW); SET_BPSW (PSW);
SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
JMP (AE_VECTOR_START); JMP (AE_VECTOR_START);
SLOT_FLUSH (); SLOT_FLUSH ();
break; break;
case SIGILL: case GDB_SIGNAL_ILL:
SET_BPC (PC); SET_BPC (PC);
SET_BPSW (PSW); SET_BPSW (PSW);
SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
@ -963,7 +960,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
iaddr = imem_addr ((uint32)PC << 2); iaddr = imem_addr ((uint32)PC << 2);
if (iaddr == State.mem.fault) if (iaddr == State.mem.fault)
{ {
State.exception = SIGBUS; State.exception = GDB_SIGNAL_BUS;
break; break;
} }
@ -1035,7 +1032,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
while ( !State.exception && !stop_simulator); while ( !State.exception && !stop_simulator);
if (step && !State.exception) if (step && !State.exception)
State.exception = SIGTRAP; State.exception = GDB_SIGNAL_TRAP;
} }
void void