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[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com> * aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case. * archures.c (bfd_mach_mipsisa32r2): New define. * bfd-in2.h: Regenerate. * cpu-mips.c (I_mipsisa32r2): New enum value. (arch_info_struct): Add entry for I_mipsisa32r2. * elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach) (_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2. (_bfd_mips_elf_final_write_processing): Add bfd_mach_mipsisa32r2 case. (_bfd_mips_elf_merge_private_bfd_data): Handle merging of binaries marked as using MIPS32 Release 2. [ binutils/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register) changes in MIPS -M options. [ gas/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * configure.in: Recognize mipsisa32r2, mipsisa32r2el, and CPU variants. * configure: Regenerate. * config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines. (macro_build): Handle "K" operand. (macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where CPU_HAS_DROR and CPU_HAS_ROR are currently used. (mips_ip): New variable "lastpos", and implement "+A", "+B", and "+C" operands for MIPS32 Release 2 ins/ext instructions. Implement "K" operand for MIPS32 Release 2 rdhwr instruction. (validate_mips_insn): Implement "+" as a way to extend the allowed operands, and implement "K", "+A", "+B", and "+C" operands. (OPTION_MIPS32R2): New define. (md_longopts): Add entry for OPTION_MIPS32R2. (OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2. (md_parse_option): Handle OPTION_MIPS32R2. (s_mipsset): Reimplement handling of ".set mipsN" options and add support for ".set mips32r2". (mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2). (md_show_usage): Document "-mips32r2" option. * doc/as.texinfo: Document "-mips32r2" option. * doc/c-mips.texi: Likewise. [ gas/testsuite/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * gas/mips/cp0-names-mips32r2.d: New test. * gas/mips/hwr-names-mips32r2.d: New test. * gas/mips/hwr-names-numeric.d: New test. * gas/mips/hwr-names.s: New test source file. * gas/mips/mips32r2.d: New test. * gas/mips/mips32r2.s: New test source file. * gas/mips/mips32r2-ill.l: New test. * gas/mips/mips32r2-ill.s: New test source file. * gas/mips/mips.exp: Add mips32r2 architecture data array entry. Run new tests mentioned above. [ include/elf/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * mips.h (E_MIPS_ARCH_32R2): New define. [ include/opcode/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * mips.h: Document "+" as the start of two-character operand type names, and add new "K", "+A", "+B", and "+C" operand types. (OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB) (OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New defines. [ opcodes/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric) (mips_hwr_names_mips3264r2): New arrays. (mips_arch_choice): New "hwr_names" member. (mips_arch_choices): Adjust for structure change, and add a new entry for "mips32r2" ISA. (mips_hwr_names): New variable. (set_default_mips_dis_options): Set mips_hwr_names. (parse_mips_dis_option): New "hwr-names" option which sets mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names. (print_insn_arg): Change return type to "int" and use that to indicate number of characters consumed. Add support for "+" operand extension character, "+A", "+B", "+C", and "K" operands. (print_insn_mips): Adjust for changes to print_insn_arg. (print_mips_disassembler_options): Adjust for "hwr-names" addition and "reg-names" change. * mips-opc (I33): New define (shorthand for INSN_ISA32R2). (mips_builtin_opcodes): Note that "nop" and "ssnop" are special forms of "sll". Add new MIPS32 Release 2 instructions: ehb, di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2, rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh. Note that hardware rotate instructions (ror, rorv) can be used on MIPS32 Release 2, and add the official mnemonics for them (rotr, rotrv) and the similar "rotl" mnemonic for left-rotate.
This commit is contained in:
Chris Demetriou
@ -4,7 +4,8 @@
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Contributed by Ralph Campbell and OSF
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Commented and modified by Ian Lance Taylor, Cygnus Support
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Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
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MIPS-3D and MDMX support added by Broadcom Corporation (SiByte).
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MIPS-3D, MDMX, and MIPS32 Release 2 support added by Broadcom
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Corporation (SiByte).
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This file is part of GDB, GAS, and the GNU binutils.
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@ -85,6 +86,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define I5 INSN_ISA5
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#define I32 INSN_ISA32
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#define I64 INSN_ISA64
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#define I33 INSN_ISA32R2
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/* MIPS64 MIPS-3D ASE support. */
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#define I16 INSN_MIPS16
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@ -137,8 +139,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
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/* name, args, match, mask, pinfo, membership */
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{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4|I32|G3 },
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{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
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{"nop", "", 0x00000000, 0xffffffff, 0, I1 },
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{"ssnop", "", 0x00000040, 0xffffffff, 0, I32|N55 },
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{"nop", "", 0x00000000, 0xffffffff, 0, I1 }, /* sll */
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{"ssnop", "", 0x00000040, 0xffffffff, 0, I32|N55 }, /* sll */
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{"ehb", "", 0x000000c0, 0xffffffff, 0, I33 }, /* sll */
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{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
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{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
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{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
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@ -478,6 +481,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 },
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{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 },
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{"deret", "", 0x4200001f, 0xffffffff, 0, I32|G2 },
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{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, I33 },
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{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, I33 },
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/* For ddiv, see the comments about div. */
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{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
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{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 },
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@ -574,7 +579,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 },
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{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
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{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 },
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{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, I33 },
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{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, I33 },
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{"eret", "", 0x42000018, 0xffffffff, 0, I3|I32 },
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{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, I33 },
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{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 },
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{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 },
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{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 },
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@ -583,7 +591,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"flushd", "", 0xbc020000, 0xffffffff, 0, L1 },
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{"flushid", "", 0xbc030000, 0xffffffff, 0, L1 },
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{"hibernate","", 0x42000023, 0xffffffff, 0, V1 },
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{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, I33 },
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{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 },
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{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, I33 },
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{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */
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/* SVR4 PIC code requires special handling for j, so it must be a
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macro. */
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@ -594,6 +604,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"j", "a", 0x08000000, 0xfc000000, UBD, I1 },
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{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 },
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{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 },
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{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, I33 },
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{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, I33 },
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/* SVR4 PIC code requires special handling for jal, so it must be a
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macro. */
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{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, I1 },
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@ -705,8 +717,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 },
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{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
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{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
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{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I33 },
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{"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I33 },
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{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
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{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 },
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{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, I33 },
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{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
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{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 },
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{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, N5 },
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@ -765,8 +780,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 },
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{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
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{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
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{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I33 },
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{"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I33 },
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{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
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{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 },
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{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, I33 },
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{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
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{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I32 },
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{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, N5 },
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@ -890,6 +908,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
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{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 },
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{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 },
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{"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, I33 },
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{"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, I33 },
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{"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 },
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{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
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{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 },
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@ -901,8 +921,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 },
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{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I1 },
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{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I1 },
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{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, N5 },
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{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, N5 },
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{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, N5|I33 },
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{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, N5|I33 },
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{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I33 },
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{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I33 },
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{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I33 },
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{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I33 },
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{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, I33 },
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{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, I3 },
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{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, I3 },
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{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 },
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@ -950,6 +975,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, I3 },
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{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, I3 },
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{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
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{"seb", "d,w", 0x7C000420, 0xffe007ff, WR_d|RD_t, I33 },
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{"seh", "d,w", 0x7C000620, 0xffe007ff, WR_d|RD_t, I33 },
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{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, L1 },
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{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, L1 },
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{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, I1 },
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@ -1057,6 +1084,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2|G1 },
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{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, I2 },
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{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2 },
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{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, I33 },
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{"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 },
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{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 },
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{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 },
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@ -1125,6 +1153,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32|N55 },
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{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
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{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
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{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, I33 },
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{"wsbh", "d,w", 0x7C0000a0, 0xffe007ff, WR_d|RD_t, I33 },
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{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
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{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
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{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
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