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PR 3134

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* h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
   with a 32-bit displacement but without the top bit of the 4th byte
   set.

   * gas/h8300/pr3134.s: New test.
   * gas/h8300/pr3134.d: Expected disassembly
   * gas/h8300/h8300.exp: Run the new test.

   * gas/h8300/h8300-coff.exp: Fix test for COFF based ports to
   accept h8300-rtemscoff not just h8300-rtems.
This commit is contained in:
Nick Clifton
2008-02-27 12:33:43 +00:00
parent b14f9da0ae
commit af7329f0ff
7 changed files with 41 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
gas/testsuite/ChangeLog
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@ -1,3 +1,13 @@
2008-02-27 Nick Clifton <nickc@redhat.com>
PR 3134
* gas/h8300/pr3134.s: New test.
* gas/h8300/pr3134.d: Expected disassembly
* gas/h8300/h8300.exp: Run the new test.
* gas/h8300/h8300-coff.exp: Fix test for COFF based ports to
accept h8300-rtemscoff not just h8300-rtems.
2008-02-26 H.J. Lu <hongjiu.lu@intel.com> 2008-02-26 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/jump.d: Updated for COFF. * gas/i386/jump.d: Updated for COFF.

2
gas/testsuite/gas/h8300/h8300-coff.exp
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@ -264,7 +264,7 @@ proc do_h8300s_branch {} {
if { [istarget h8300*-*-coff] if { [istarget h8300*-*-coff]
|| [istarget h8300*-*-hms*] || [istarget h8300*-*-hms*]
|| [istarget h8300*-*-rtems*] } then { || [istarget h8300*-*-rtemscoff*] } then {
# Test the basic h8300 instruction parser # Test the basic h8300 instruction parser
do_h8300_cbranch do_h8300_cbranch

2
gas/testsuite/gas/h8300/h8300.exp
View File

@ -2244,4 +2244,6 @@ if [istarget h8300*-*-*] then {
set aout [expr [istarget *-*-bsd*] || [istarget *-*-netbsd*]] set aout [expr [istarget *-*-bsd*] || [istarget *-*-netbsd*]]
gas_test "cmpsi2.s" "" "" "cmpsi2.s" gas_test "cmpsi2.s" "" "" "cmpsi2.s"
run_dump_test "pr3134"
} }

11
gas/testsuite/gas/h8300/pr3134.d Normal file
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@ -0,0 +1,11 @@
# objdump: -wd
# name: Check that both encodings of mov.l (disp32) are accepted (PR 3134)
.*: *file format elf32-h8300.*
Disassembly of section \.text:
0+00 <\.text>:
.*:[ ]+01 00 78 80 6b a0 00 00 00 00[ ]+mov.l[ ]+er0,@\(0x0:32,er0\)
.*:[ ]+01 00 78 80 6b a0 00 00 00 00[ ]+mov.l[ ]+er0,@\(0x0:32,er0\)
.*:[ ]+01 00 78 00 6b a0 00 00 00 00[ ]+mov.l[ ]+er0,@\(0x0:32,er0\)

7
gas/testsuite/gas/h8300/pr3134.s Normal file
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@ -0,0 +1,7 @@
.h8300s
mov er0, @(0:32,er0)
.byte 1, 0, 0x78, 0x80, 0x6b, 0xa0, 0, 0, 0, 0
.byte 1, 0, 0x78, 0x00, 0x6b, 0xa0, 0, 0, 0, 0

8
include/opcode/ChangeLog
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@ -1,3 +1,11 @@
2008-02-27 Markus Gyger <markus+sw@gyger.org>
Nick Clifton <nickc@redhat.com>
PR 3134
* h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
with a 32-bit displacement but without the top bit of the 4th byte
set.
2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com> 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
* cr16.h (cr16_num_optab): Declared. * cr16.h (cr16_num_optab): Declared.

3
include/opcode/h8300.h
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@ -1,6 +1,6 @@
/* Opcode table for the H8/300 /* Opcode table for the H8/300
Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2001, 2002, Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2001, 2002,
2003, 2004 2003, 2004, 2008
Free Software Foundation, Inc. Free Software Foundation, Inc.
Written by Steve Chamberlain <sac@cygnus.com>. Written by Steve Chamberlain <sac@cygnus.com>.
@ -1519,6 +1519,7 @@ struct h8_opcode h8_opcodes[] =
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},