[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions

This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.

This patch adds the following:
MSR Xn, RNDR
MSR Xn, RNDRRS

These are optional instructions in ARMv8.5-A and hence the new
+rng is added.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_RNG): New.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): New entries for
	rndr and rndrrs.
	(aarch64_sys_reg_supported_p): New check for above.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (aarch64_features): New "rng" option.
	* doc/c-aarch64.texi: Document the same.
	* testsuite/gas/aarch64/sysreg-4.s: Test both instructions.
	* testsuite/gas/aarch64/sysreg-4.d: Likewise.
	* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.

gas/ChangeLog

@@ -1,3 +1,11 @@
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* config/tc-aarch64.c (aarch64_features): New "rng" option.
+	* doc/c-aarch64.texi: Document the same.
+	* testsuite/gas/aarch64/sysreg-4.s: Test both instructions.
+	* testsuite/gas/aarch64/sysreg-4.d: Likewise.
+	* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
+
 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 
 	* testsuite/gas/aarch64/sysreg-4.s: Test instruction.

gas/config/tc-aarch64.c

@@ -8773,6 +8773,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"sha3",		AARCH64_FEATURE (AARCH64_FEATURE_SHA2
 					 | AARCH64_FEATURE_SHA3, 0),
 			AARCH64_ARCH_NONE},
+  {"rng",		AARCH64_FEATURE (AARCH64_FEATURE_RNG, 0),
+			AARCH64_ARCH_NONE},
   {NULL,		AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
 };
 

gas/doc/c-aarch64.texi

@@ -185,6 +185,8 @@ automatically cause those extensions to be disabled.
  @tab Enable the speculation barrier instruction sb.
 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
  @tab Enable the Execution and Data and Prediction instructions.
+@item @code{rng} @tab ARMv8.5-A @tab No
+ @tab Enable ARMv8.5-A random number instructions.
 @end multitable
 
 @node AArch64 Syntax

gas/testsuite/gas/aarch64/illegal-sysreg-4.l

@@ -6,3 +6,5 @@
 [^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
 [^:]*:[0-9]+: Error: selected processor does not support `cpp rctx,x3'
 [^:]*:[0-9]+: Error: selected processor does not support system register name 'cvadp'
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rndr'
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rndrrs'

gas/testsuite/gas/aarch64/sysreg-4.d

@@ -1,5 +1,5 @@
 #source: sysreg-4.s
-#as: -march=armv8.5-a
+#as: -march=armv8.5-a+rng
 #objdump: -dr
 
 .*:     file format .*
@@ -11,3 +11,5 @@ Disassembly of section \.text:
 .*:	d50b73a2 	dvp	rctx, x2
 .*:	d50b73e3 	cpp	rctx, x3
 .*:	d50b7d24 	dc	cvadp, x4
+.*:	d53b2405 	mrs	x5, rndr
+.*:	d53b2426 	mrs	x6, rndrrs

gas/testsuite/gas/aarch64/sysreg-4.s

@@ -4,3 +4,5 @@ func:
 	dvp rctx, x2
 	cpp rctx, x3
 	dc cvadp, x4
+	mrs x5, rndr
+	mrs x6, rndrrs

include/ChangeLog

@@ -1,3 +1,7 @@
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (AARCH64_FEATURE_RNG): New.
+
 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 
 	* opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.

include/opcode/aarch64.h

@@ -74,6 +74,8 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_PREDRES		0x20000000000ULL
 /* DC CVADP.  */
 #define AARCH64_FEATURE_CVADP		0x40000000000ULL
+/* Random Number instructions.  */
+#define AARCH64_FEATURE_RNG		0x80000000000ULL
 
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8		AARCH64_FEATURE (AARCH64_FEATURE_V8, \

opcodes/ChangeLog

@@ -1,3 +1,9 @@
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* aarch64-opc.c (aarch64_sys_regs): New entries for
+	rndr and rndrrs.
+	(aarch64_sys_reg_supported_p): New check for above.
+
 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 
 	* aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.

opcodes/aarch64-opc.c

@@ -3855,6 +3855,8 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   { "contextidr_el1",   CPENC(3,0,C13,C0,1),	0 },
   { "contextidr_el2",	CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
   { "contextidr_el12",	CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
+  { "rndr",		CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
+  { "rndrrs",		CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
   { "tpidr_el0",        CPENC(3,3,C13,C0,2),	0 },
   { "tpidrro_el0",      CPENC(3,3,C13,C0,3),	0 }, /* RW */
   { "tpidr_el1",        CPENC(3,0,C13,C0,4),	0 },
@@ -4286,6 +4288,14 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
     return FALSE;
 
+  /* Random Number Instructions.  For now they are available
+     (and optional) only with ARMv8.5-A.  */
+  if ((reg->value == CPENC (3, 3, C2, C4, 0)
+       || reg->value == CPENC (3, 3, C2, C4, 1))
+      && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RNG)
+	   && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_5)))
+    return FALSE;
+
   return TRUE;
 }