mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-06-01 20:12:01 +08:00
* gencode.c (movua.l): Compensate for endianness.
* interp.c (RAISE_EXCEPTION_IF_IN_DELAY_SLOT): New macro. (in_delay_slot): New flag variable. (Delay_Slot): Set in_delay_slot. (sim_resume): Reset in_delay_slot after leaving code switch. * gencode.c (op tab): Call RAISE_EXCEPTION_IF_IN_DELAY_SLOT for all instructions not allowed in delay slots. Commited by Corinna Vinschen <vinschen@redhat.com> Introduce SH2a support. * interp.c: Change type of jump table to short. Add various macros. (sim_load): Save the bfd machine code. (sim_create_inferior): Ditto. (union saved_state_type): Add tbr, ibnr and ibcr registers. Move bfd_mach to end of struct. Add regstack pointer. (init_dsp): Don't swap contents of sh_dsp_table any more. Instead use it directly in its own switch statement. Allocate space for 512 register banks. (do_long_move_insn): New function. (do_blog_insn): Ditto. (trap): Use trap #13 and trap #14 to set ibnr and ibcr. * gencode.c: Move movx/movy insns into separate switch statement. (op tab): Add sh2a insns. Reject instructions that are disabled on that chip. (gensim_caselist): Generate default case here instead of in caller. (gensim): Generate two separate switch statements. Call gensim_caselist once for each (for movsxy_tab and for tab). Add tokens for r15 and multiple regs. (conflict_warn, warn_conflicts): Add for debugging.
This commit is contained in:
Corinna Vinschen
344
sim/sh/interp.c
344
sim/sh/interp.c
@ -65,6 +65,11 @@ int sim_write (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size);
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for a quit. */
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#define POLL_QUIT_INTERVAL 0x60000
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typedef struct
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{
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int regs[20];
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} regstacktype;
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typedef union
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{
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@ -123,6 +128,9 @@ typedef union
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int dbr; /* debug base register */
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int sgr; /* saved gr15 */
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int ldst; /* load/store flag (boolean) */
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int tbr;
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int ibcr; /* sh2a bank control register */
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int ibnr; /* sh2a bank number register */
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} named;
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int i[16];
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} cregs;
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@ -152,6 +160,8 @@ typedef union
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unsigned char *ymem;
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unsigned char *xmem_offset;
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unsigned char *ymem_offset;
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unsigned long bfd_mach;
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regstacktype *regstack;
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}
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asregs;
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int asints[40];
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@ -175,6 +185,7 @@ static int maskl = 0;
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static SIM_OPEN_KIND sim_kind;
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static char *myname;
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static int tracing = 0;
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/* Short hand definitions of the registers */
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@ -191,6 +202,11 @@ static char *myname;
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#define GBR saved_state.asregs.cregs.named.gbr
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#define VBR saved_state.asregs.cregs.named.vbr
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#define DBR saved_state.asregs.cregs.named.dbr
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#define TBR saved_state.asregs.cregs.named.tbr
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#define IBCR saved_state.asregs.cregs.named.ibcr
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#define IBNR saved_state.asregs.cregs.named.ibnr
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#define BANKN (saved_state.asregs.cregs.named.ibnr & 0x1ff)
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#define ME ((saved_state.asregs.cregs.named.ibnr >> 14) & 0x3)
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#define SSR saved_state.asregs.cregs.named.ssr
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#define SPC saved_state.asregs.cregs.named.spc
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#define SGR saved_state.asregs.cregs.named.sgr
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@ -213,6 +229,8 @@ static char *myname;
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/* Manipulate SR */
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#define SR_MASK_BO (1 << 14)
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#define SR_MASK_CS (1 << 13)
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#define SR_MASK_DMY (1 << 11)
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#define SR_MASK_DMX (1 << 10)
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#define SR_MASK_M (1 << 9)
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@ -227,6 +245,8 @@ static char *myname;
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#define SR_MASK_RC 0x0fff0000
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#define SR_RC_INCREMENT -0x00010000
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#define BO ((saved_state.asregs.cregs.named.sr & SR_MASK_BO) != 0)
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#define CS ((saved_state.asregs.cregs.named.sr & SR_MASK_CS) != 0)
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#define M ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
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#define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
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#define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
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@ -249,6 +269,16 @@ do { \
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saved_state.asregs.cregs.named.sr &= ~(BIT); \
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} while (0)
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#define SET_SR_BO(EXP) SET_SR_BIT ((EXP), SR_MASK_BO)
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#define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS)
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#define SET_BANKN(EXP) \
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do { \
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IBNR = (IBNR & 0xfe00) | (EXP & 0x1f); \
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} while (0)
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#define SET_ME(EXP) \
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do { \
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IBNR = (IBNR & 0x3fff) | ((EXP & 0x3) << 14); \
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} while (0)
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#define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
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#define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
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#define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
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@ -323,6 +353,9 @@ fail ()
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#define RAISE_EXCEPTION(x) \
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(saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
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#define RAISE_EXCEPTION_IF_IN_DELAY_SLOT() \
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if (in_delay_slot) RAISE_EXCEPTION (SIGILL)
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/* This function exists mainly for the purpose of setting a breakpoint to
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catch simulated bus errors when running the simulator under GDB. */
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@ -780,7 +813,8 @@ process_rbat_addr (addr)
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#define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
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#define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); goto top;
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static int in_delay_slot = 0;
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#define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); in_delay_slot = 1; goto top;
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#define CHECK_INSN_PTR(p) \
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do { \
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@ -1181,6 +1215,12 @@ trap (i, regs, insn_ptr, memory, maskl, maskw, endianw)
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}
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break;
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case 13: /* Set IBNR */
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IBNR = regs[0] & 0xffff;
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break;
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case 14: /* Set IBCR */
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IBCR = regs[0] & 0xffff;
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break;
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case 0xc3:
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case 255:
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raise_exception (SIGTRAP);
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@ -1419,32 +1459,140 @@ macl (regs, memory, n, m)
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MACH = mach;
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}
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enum {
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B_BCLR = 0,
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B_BSET = 1,
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B_BST = 2,
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B_BLD = 3,
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B_BAND = 4,
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B_BOR = 5,
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B_BXOR = 6,
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B_BLDNOT = 11,
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B_BANDNOT = 12,
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B_BORNOT = 13,
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MOVB_RM = 0x0000,
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MOVW_RM = 0x1000,
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MOVL_RM = 0x2000,
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FMOV_RM = 0x3000,
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MOVB_MR = 0x4000,
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MOVW_MR = 0x5000,
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MOVL_MR = 0x6000,
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FMOV_MR = 0x7000,
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MOVU_BMR = 0x8000,
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MOVU_WMR = 0x9000,
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};
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/* GET_LOOP_BOUNDS {EXTENDED}
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These two functions compute the actual starting and ending point
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of the repeat loop, based on the RS and RE registers (repeat start,
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repeat stop). The extended version is called for LDRC, and the
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regular version is called for SETRC. The difference is that for
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LDRC, the loop start and end instructions are literally the ones
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pointed to by RS and RE -- for SETRC, they're not (see docs). */
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static struct loop_bounds
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get_loop_bounds_ext (rs, re, memory, mem_end, maskw, endianw)
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int rs, re;
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unsigned char *memory, *mem_end;
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int maskw, endianw;
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/* Do extended displacement move instructions. */
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void
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do_long_move_insn (int op, int disp12, int m, int n, int *thatlock)
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{
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struct loop_bounds loop;
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int memstalls = 0;
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int thislock = *thatlock;
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int endianw = global_endianw;
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int *R = &(saved_state.asregs.regs[0]);
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unsigned char *memory = saved_state.asregs.memory;
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int maskb = ~((saved_state.asregs.msize - 1) & ~0);
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unsigned char *insn_ptr = PT2H (saved_state.asregs.pc);
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/* FIXME: should I verify RS < RE? */
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loop.start = PT2H (RS); /* FIXME not using the params? */
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loop.end = PT2H (RE & ~1); /* Ignore bit 0 of RE. */
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SKIP_INSN (loop.end);
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if (loop.end >= mem_end)
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loop.end = PT2H (0);
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return loop;
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switch (op) {
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case MOVB_RM: /* signed */
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WBAT (disp12 * 1 + R[n], R[m]);
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break;
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case MOVW_RM:
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WWAT (disp12 * 2 + R[n], R[m]);
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break;
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case MOVL_RM:
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WLAT (disp12 * 4 + R[n], R[m]);
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break;
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case FMOV_RM: /* floating point */
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if (FPSCR_SZ)
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{
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MA (1);
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WDAT (R[n] + 8 * disp12, m);
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}
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else
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WLAT (R[n] + 4 * disp12, FI (m));
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break;
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case MOVB_MR:
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R[n] = RSBAT (disp12 * 1 + R[m]);
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L (n);
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break;
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case MOVW_MR:
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R[n] = RSWAT (disp12 * 2 + R[m]);
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L (n);
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break;
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case MOVL_MR:
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R[n] = RLAT (disp12 * 4 + R[m]);
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L (n);
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break;
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case FMOV_MR:
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if (FPSCR_SZ) {
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MA (1);
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RDAT (R[m] + 8 * disp12, n);
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}
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else
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SET_FI (n, RLAT (R[m] + 4 * disp12));
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break;
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case MOVU_BMR: /* unsigned */
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R[n] = RBAT (disp12 * 1 + R[m]);
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L (n);
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break;
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case MOVU_WMR:
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R[n] = RWAT (disp12 * 2 + R[m]);
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L (n);
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break;
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default:
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RAISE_EXCEPTION (SIGINT);
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exit (1);
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}
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saved_state.asregs.memstalls += memstalls;
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*thatlock = thislock;
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}
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/* Do binary logical bit-manipulation insns. */
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void
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do_blog_insn (int imm, int addr, int binop,
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unsigned char *memory, int maskb)
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{
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int oldval = RBAT (addr);
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switch (binop) {
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case B_BCLR: /* bclr.b */
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WBAT (addr, oldval & ~imm);
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break;
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case B_BSET: /* bset.b */
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WBAT (addr, oldval | imm);
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break;
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case B_BST: /* bst.b */
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if (T)
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WBAT (addr, oldval | imm);
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else
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WBAT (addr, oldval & ~imm);
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break;
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case B_BLD: /* bld.b */
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SET_SR_T ((oldval & imm) != 0);
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break;
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case B_BAND: /* band.b */
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SET_SR_T (T && ((oldval & imm) != 0));
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break;
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case B_BOR: /* bor.b */
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SET_SR_T (T || ((oldval & imm) != 0));
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break;
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case B_BXOR: /* bxor.b */
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SET_SR_T (T ^ ((oldval & imm) != 0));
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break;
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case B_BLDNOT: /* bldnot.b */
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SET_SR_T ((oldval & imm) == 0);
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break;
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case B_BANDNOT: /* bandnot.b */
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SET_SR_T (T && ((oldval & imm) == 0));
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break;
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case B_BORNOT: /* bornot.b */
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SET_SR_T (T || ((oldval & imm) == 0));
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break;
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}
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}
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float
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fsca_s (int in, double (*f) (double))
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{
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@ -1494,6 +1642,32 @@ fsrra_s (float in)
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return upper - result >= result - lower ? upper : lower;
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}
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/* GET_LOOP_BOUNDS {EXTENDED}
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These two functions compute the actual starting and ending point
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of the repeat loop, based on the RS and RE registers (repeat start,
|
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repeat stop). The extended version is called for LDRC, and the
|
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regular version is called for SETRC. The difference is that for
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LDRC, the loop start and end instructions are literally the ones
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pointed to by RS and RE -- for SETRC, they're not (see docs). */
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static struct loop_bounds
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get_loop_bounds_ext (rs, re, memory, mem_end, maskw, endianw)
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int rs, re;
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unsigned char *memory, *mem_end;
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int maskw, endianw;
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{
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struct loop_bounds loop;
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/* FIXME: should I verify RS < RE? */
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loop.start = PT2H (RS); /* FIXME not using the params? */
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loop.end = PT2H (RE & ~1); /* Ignore bit 0 of RE. */
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SKIP_INSN (loop.end);
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if (loop.end >= mem_end)
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loop.end = PT2H (0);
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return loop;
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}
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static struct loop_bounds
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get_loop_bounds (rs, re, memory, mem_end, maskw, endianw)
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int rs, re;
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@ -1607,8 +1781,10 @@ init_dsp (abfd)
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saved_state.asregs.xyram_select = new_select;
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free (saved_state.asregs.xmem);
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free (saved_state.asregs.ymem);
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saved_state.asregs.xmem = (unsigned char *) calloc (1, ram_area_size);
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saved_state.asregs.ymem = (unsigned char *) calloc (1, ram_area_size);
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saved_state.asregs.xmem =
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(unsigned char *) calloc (1, ram_area_size);
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saved_state.asregs.ymem =
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(unsigned char *) calloc (1, ram_area_size);
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/* Disable use of X / Y mmeory if not allocated. */
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if (! saved_state.asregs.xmem || ! saved_state.asregs.ymem)
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@ -1642,6 +1818,10 @@ init_dsp (abfd)
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saved_state.asregs.yram_start = 1;
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}
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if (saved_state.asregs.regstack == NULL)
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saved_state.asregs.regstack =
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calloc (512, sizeof *saved_state.asregs.regstack);
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if (target_dsp != was_dsp)
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{
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int i, tmp;
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@ -1741,7 +1921,11 @@ sim_resume (sd, step, siggnal)
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register int memstalls = 0;
|
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register int insts = 0;
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register int prevlock;
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#if 1
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int thislock;
|
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#else
|
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register int thislock;
|
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#endif
|
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register unsigned int doprofile;
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register int pollcount = 0;
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/* endianw is used for every insn fetch, hence it makes sense to cache it.
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@ -1820,10 +2004,13 @@ sim_resume (sd, step, siggnal)
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insts++;
|
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#endif
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top:
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if (tracing)
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fprintf (stderr, "PC: %08x, insn: %04x\n", PH2T (insn_ptr), iword);
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|
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#include "code.c"
|
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|
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|
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in_delay_slot = 0;
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insn_ptr = nip;
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|
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if (--pollcount < 0)
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@ -1940,6 +2127,15 @@ sim_read (sd, addr, buffer, size)
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return size;
|
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}
|
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|
||||
static int gdb_bank_number;
|
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enum {
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REGBANK_MACH = 15,
|
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REGBANK_IVN = 16,
|
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REGBANK_PR = 17,
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REGBANK_GBR = 18,
|
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REGBANK_MACL = 19
|
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};
|
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|
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int
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sim_store_register (sd, rn, memory, length)
|
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SIM_DESC sd;
|
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@ -2050,6 +2246,12 @@ sim_store_register (sd, rn, memory, length)
|
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case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM:
|
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case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM:
|
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case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM:
|
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if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
|
||||
{
|
||||
rn -= SIM_SH_R0_BANK0_REGNUM;
|
||||
saved_state.asregs.regstack[gdb_bank_number].regs[rn] = val;
|
||||
}
|
||||
else
|
||||
if (SR_MD && SR_RB)
|
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Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) = val;
|
||||
else
|
||||
@ -2059,6 +2261,12 @@ sim_store_register (sd, rn, memory, length)
|
||||
case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM:
|
||||
case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM:
|
||||
case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM:
|
||||
if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
|
||||
{
|
||||
rn -= SIM_SH_R0_BANK1_REGNUM;
|
||||
saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8] = val;
|
||||
}
|
||||
else
|
||||
if (SR_MD && SR_RB)
|
||||
saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM] = val;
|
||||
else
|
||||
@ -2070,6 +2278,35 @@ sim_store_register (sd, rn, memory, length)
|
||||
case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM:
|
||||
SET_Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM, val);
|
||||
break;
|
||||
case SIM_SH_TBR_REGNUM:
|
||||
TBR = val;
|
||||
break;
|
||||
case SIM_SH_IBNR_REGNUM:
|
||||
IBNR = val;
|
||||
break;
|
||||
case SIM_SH_IBCR_REGNUM:
|
||||
IBCR = val;
|
||||
break;
|
||||
case SIM_SH_BANK_REGNUM:
|
||||
/* This is a pseudo-register maintained just for gdb.
|
||||
It tells us what register bank gdb would like to read/write. */
|
||||
gdb_bank_number = val;
|
||||
break;
|
||||
case SIM_SH_BANK_MACL_REGNUM:
|
||||
saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL] = val;
|
||||
break;
|
||||
case SIM_SH_BANK_GBR_REGNUM:
|
||||
saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR] = val;
|
||||
break;
|
||||
case SIM_SH_BANK_PR_REGNUM:
|
||||
saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR] = val;
|
||||
break;
|
||||
case SIM_SH_BANK_IVN_REGNUM:
|
||||
saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN] = val;
|
||||
break;
|
||||
case SIM_SH_BANK_MACH_REGNUM:
|
||||
saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH] = val;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
@ -2185,6 +2422,12 @@ sim_fetch_register (sd, rn, memory, length)
|
||||
case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM:
|
||||
case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM:
|
||||
case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM:
|
||||
if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
|
||||
{
|
||||
rn -= SIM_SH_R0_BANK0_REGNUM;
|
||||
val = saved_state.asregs.regstack[gdb_bank_number].regs[rn];
|
||||
}
|
||||
else
|
||||
val = (SR_MD && SR_RB
|
||||
? Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM)
|
||||
: saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM]);
|
||||
@ -2193,6 +2436,12 @@ sim_fetch_register (sd, rn, memory, length)
|
||||
case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM:
|
||||
case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM:
|
||||
case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM:
|
||||
if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
|
||||
{
|
||||
rn -= SIM_SH_R0_BANK1_REGNUM;
|
||||
val = saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8];
|
||||
}
|
||||
else
|
||||
val = (! SR_MD || ! SR_RB
|
||||
? Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM)
|
||||
: saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM]);
|
||||
@ -2203,6 +2452,35 @@ sim_fetch_register (sd, rn, memory, length)
|
||||
case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM:
|
||||
val = Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM);
|
||||
break;
|
||||
case SIM_SH_TBR_REGNUM:
|
||||
val = TBR;
|
||||
break;
|
||||
case SIM_SH_IBNR_REGNUM:
|
||||
val = IBNR;
|
||||
break;
|
||||
case SIM_SH_IBCR_REGNUM:
|
||||
val = IBCR;
|
||||
break;
|
||||
case SIM_SH_BANK_REGNUM:
|
||||
/* This is a pseudo-register maintained just for gdb.
|
||||
It tells us what register bank gdb would like to read/write. */
|
||||
val = gdb_bank_number;
|
||||
break;
|
||||
case SIM_SH_BANK_MACL_REGNUM:
|
||||
val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL];
|
||||
break;
|
||||
case SIM_SH_BANK_GBR_REGNUM:
|
||||
val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR];
|
||||
break;
|
||||
case SIM_SH_BANK_PR_REGNUM:
|
||||
val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR];
|
||||
break;
|
||||
case SIM_SH_BANK_IVN_REGNUM:
|
||||
val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN];
|
||||
break;
|
||||
case SIM_SH_BANK_MACH_REGNUM:
|
||||
val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH];
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
@ -2214,7 +2492,10 @@ int
|
||||
sim_trace (sd)
|
||||
SIM_DESC sd;
|
||||
{
|
||||
return 0;
|
||||
tracing = 1;
|
||||
sim_resume (sd, 0, 0);
|
||||
tracing = 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
void
|
||||
@ -2381,6 +2662,15 @@ sim_load (sd, prog, abfd, from_tty)
|
||||
prog_bfd = sim_load_file (sd, myname, callback, prog, abfd,
|
||||
sim_kind == SIM_OPEN_DEBUG,
|
||||
0, sim_write);
|
||||
|
||||
/* Set the bfd machine type. */
|
||||
if (prog_bfd)
|
||||
saved_state.asregs.bfd_mach = bfd_get_mach (prog_bfd);
|
||||
else if (abfd)
|
||||
saved_state.asregs.bfd_mach = bfd_get_mach (abfd);
|
||||
else
|
||||
saved_state.asregs.bfd_mach = 0;
|
||||
|
||||
if (prog_bfd == NULL)
|
||||
return SIM_RC_FAIL;
|
||||
if (abfd == NULL)
|
||||
@ -2403,6 +2693,10 @@ sim_create_inferior (sd, prog_bfd, argv, env)
|
||||
if (prog_bfd != NULL)
|
||||
saved_state.asregs.pc = bfd_get_start_address (prog_bfd);
|
||||
|
||||
/* Set the bfd machine type. */
|
||||
if (prog_bfd != NULL)
|
||||
saved_state.asregs.bfd_mach = bfd_get_mach (prog_bfd);
|
||||
|
||||
/* Record the program's arguments. */
|
||||
prog_argv = argv;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user