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https://github.com/espressif/binutils-gdb.git
synced 2025-08-06 14:49:38 +08:00
Add "attn", "lq" and "stq" power4 insns.
This commit is contained in:
Alan Modra
@ -68,6 +68,10 @@ static unsigned long insert_boe
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PARAMS ((unsigned long, long, int, const char **));
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static long extract_boe
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PARAMS ((unsigned long, int, int *));
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static unsigned long insert_dq
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PARAMS ((unsigned long, long, int, const char **));
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static long extract_dq
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PARAMS ((unsigned long, int, int *));
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static unsigned long insert_ds
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PARAMS ((unsigned long, long, int, const char **));
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static long extract_ds
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@ -104,12 +108,18 @@ static unsigned long insert_ral
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PARAMS ((unsigned long, long, int, const char **));
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static unsigned long insert_ram
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PARAMS ((unsigned long, long, int, const char **));
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static unsigned long insert_raq
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PARAMS ((unsigned long, long, int, const char **));
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static unsigned long insert_ras
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PARAMS ((unsigned long, long, int, const char **));
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static unsigned long insert_rbs
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PARAMS ((unsigned long, long, int, const char **));
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static long extract_rbs
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PARAMS ((unsigned long, int, int *));
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static unsigned long insert_rsq
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PARAMS ((unsigned long, long, int, const char **));
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static unsigned long insert_rtq
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PARAMS ((unsigned long, long, int, const char **));
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static unsigned long insert_sh6
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PARAMS ((unsigned long, long, int, const char **));
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static long extract_sh6
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@ -279,9 +289,15 @@ const struct powerpc_operand powerpc_operands[] =
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#define DES DE + 1
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{ 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
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/* The DQ field in a DQ form instruction. This is like D, but the
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lower four bits are forced to zero. */
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#define DQ DES + 1
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{ 16, 0, insert_dq, extract_dq,
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PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
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/* The DS field in a DS form instruction. This is like D, but the
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lower two bits are forced to zero. */
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#define DS DES + 1
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#define DS DQ + 1
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{ 16, 0, insert_ds, extract_ds,
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PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
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@ -389,15 +405,20 @@ const struct powerpc_operand powerpc_operands[] =
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{ 16, 0, insert_nsi, extract_nsi,
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PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
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/* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
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/* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
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#define RA NSI + 1
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#define RA_MASK (0x1f << 16)
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{ 5, 16, 0, 0, PPC_OPERAND_GPR },
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/* The RA field in the DQ form lq instruction, which has special
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value restrictions. */
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#define RAQ RA + 1
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{ 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
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/* The RA field in a D or X form instruction which is an updating
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load, which means that the RA field may not be zero and may not
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equal the RT field. */
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#define RAL RA + 1
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#define RAL RAQ + 1
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{ 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
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/* The RA field in an lmw instruction, which has special value
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@ -430,8 +451,18 @@ const struct powerpc_operand powerpc_operands[] =
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#define RT_MASK (0x1f << 21)
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{ 5, 21, 0, 0, PPC_OPERAND_GPR },
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/* The RS field of the DS form stq instruction, which has special
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value restrictions. */
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#define RSQ RS + 1
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{ 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
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/* The RT field of the DQ form lq instruction, which has special
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value restrictions. */
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#define RTQ RSQ + 1
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{ 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
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/* The SH field in an X or M form instruction. */
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#define SH RS + 1
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#define SH RTQ + 1
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#define SH_MASK (0x1f << 11)
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{ 5, 11, 0, 0, 0 },
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@ -870,6 +901,32 @@ extract_boe (insn, dialect, invalid)
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return value & 0x1e;
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}
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/* The DQ field in a DQ form instruction. This is like D, but the
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lower four bits are forced to zero. */
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/*ARGSUSED*/
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static unsigned long
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insert_dq (insn, value, dialect, errmsg)
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unsigned long insn;
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long value;
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int dialect ATTRIBUTE_UNUSED;
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const char ** errmsg ATTRIBUTE_UNUSED;
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{
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if ((value & 0xf) != 0 && errmsg != NULL)
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*errmsg = _("offset not a multiple of 16");
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return insn | (value & 0xfff0);
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}
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/*ARGSUSED*/
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static long
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extract_dq (insn, dialect, invalid)
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unsigned long insn;
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int dialect ATTRIBUTE_UNUSED;
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int *invalid ATTRIBUTE_UNUSED;
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{
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return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
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}
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static unsigned long
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insert_ev2 (insn, value, dialect, errmsg)
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unsigned long insn;
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@ -1253,6 +1310,24 @@ insert_ram (insn, value, dialect, errmsg)
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return insn | ((value & 0x1f) << 16);
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}
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/* The RA field in the DQ form lq instruction, which has special
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value restrictions. */
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/*ARGSUSED*/
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static unsigned long
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insert_raq (insn, value, dialect, errmsg)
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unsigned long insn;
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long value;
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int dialect ATTRIBUTE_UNUSED;
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const char **errmsg;
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{
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long rtvalue = (insn & RT_MASK) >> 21;
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if (value == rtvalue && errmsg != NULL)
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*errmsg = _("source and target register operands must be different");
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return insn | ((value & 0x1f) << 16);
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}
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/* The RA field in a D or X form instruction which is an updating
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store or an updating floating point load, which means that the RA
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field may not be zero. */
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@ -1298,6 +1373,38 @@ extract_rbs (insn, dialect, invalid)
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return 0;
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}
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/* The RT field of the DQ form lq instruction, which has special
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value restrictions. */
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/*ARGSUSED*/
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static unsigned long
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insert_rtq (insn, value, dialect, errmsg)
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unsigned long insn;
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long value;
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int dialect ATTRIBUTE_UNUSED;
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const char **errmsg;
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{
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if ((value & 1) != 0 && errmsg != NULL)
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*errmsg = _("target register operand must be even");
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return insn | ((value & 0x1f) << 21);
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}
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/* The RS field of the DS form stq instruction, which has special
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value restrictions. */
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/*ARGSUSED*/
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static unsigned long
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insert_rsq (insn, value, dialect, errmsg)
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unsigned long insn;
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long value ATTRIBUTE_UNUSED;
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int dialect ATTRIBUTE_UNUSED;
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const char **errmsg;
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{
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if ((value & 1) != 0 && errmsg != NULL)
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*errmsg = _("source register operand must be even");
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return insn | ((value & 0x1f) << 21);
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}
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/* The SH field in an MD form instruction. This is split. */
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/*ARGSUSED*/
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@ -1768,6 +1875,7 @@ extract_tbr (insn, dialect, invalid)
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sorted by major opcode. */
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const struct powerpc_opcode powerpc_opcodes[] = {
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{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
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{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
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{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
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{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
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@ -4335,6 +4443,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
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{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
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{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
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{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
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@ -4411,6 +4521,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
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{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } },
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{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
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{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
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