diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index d839fdc587a..09d1c165ad0 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,15 @@
+2010-07-05 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * gas/mips/mips4-fp.d, gas/mips/mips4-fp.s: Remove checks for
+ branch-likely instructions and place them...
+ * gas/mips/mips4-branch-likely.d, gas/mips/mips4-branch-likely.s:
+ ... in this new test.
+ * gas/mips/mips4-fp.l: Update accordingly.
+ * gas/mips/mips4-branch-likely.l: New stderr output for the new
+ test.
+ * gas/mips/mips.exp (mips4-branch-likely): Run a dump test and
+ a list test with mips4-branch-likely similarly to mips4-fp.
+
2010-07-05 Maciej W. Rozycki <macro@codesourcery.com>
* gas/mips/beq.d, gas/mips/beq.s: Remove checks for
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 53748754622..f14c6ffea44 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -484,6 +484,10 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "mips4-fp" [mips_arch_list_matching mips4]
run_list_test_arches "mips4-fp" "-32 -msoft-float" \
[mips_arch_list_matching mips4]
+ run_dump_test_arches "mips4-branch-likely" \
+ [mips_arch_list_matching mips4]
+ run_list_test_arches "mips4-branch-likely" "-32 -msoft-float" \
+ [mips_arch_list_matching mips4]
run_dump_test_arches "mips5" [mips_arch_list_matching mips5]
run_dump_test "mul"
diff --git a/gas/testsuite/gas/mips/mips4-branch-likely.d b/gas/testsuite/gas/mips/mips4-branch-likely.d
new file mode 100644
index 00000000000..222bd30c887
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips4-branch-likely.d
@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS mips4 branch-likely instructions
+
+# Test mips4 branch-likely instructions.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> bc1fl \$fcc1,0+0000 <text_label>
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bc1tl \$fcc2,0+0000 <text_label>
+[0-9a-f]+ <[^>]*> nop
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/mips4-branch-likely.l b/gas/testsuite/gas/mips/mips4-branch-likely.l
new file mode 100644
index 00000000000..0e0cc587e05
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips4-branch-likely.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `bc1fl \$fcc1,text_label'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `bc1tl \$fcc2,text_label'
diff --git a/gas/testsuite/gas/mips/mips4-branch-likely.s b/gas/testsuite/gas/mips/mips4-branch-likely.s
new file mode 100644
index 00000000000..7eb4f656069
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips4-branch-likely.s
@@ -0,0 +1,9 @@
+# Source file used to test -mips4 branch-likely instructions.
+
+ .text
+text_label:
+ bc1fl $fcc1,text_label
+ bc1tl $fcc2,text_label
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
diff --git a/gas/testsuite/gas/mips/mips4-fp.d b/gas/testsuite/gas/mips/mips4-fp.d
index 8082d611245..23a9119dde4 100644
--- a/gas/testsuite/gas/mips/mips4-fp.d
+++ b/gas/testsuite/gas/mips/mips4-fp.d
@@ -10,12 +10,8 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> nop
[0-9a-f]+ <[^>]*> bc1f \$fcc1,0+0000 <text_label>
[0-9a-f]+ <[^>]*> nop
-[0-9a-f]+ <[^>]*> bc1fl \$fcc1,0+0000 <text_label>
-[0-9a-f]+ <[^>]*> nop
[0-9a-f]+ <[^>]*> bc1t \$fcc1,0+0000 <text_label>
[0-9a-f]+ <[^>]*> nop
-[0-9a-f]+ <[^>]*> bc1tl \$fcc2,0+0000 <text_label>
-[0-9a-f]+ <[^>]*> nop
[0-9a-f]+ <[^>]*> c.f.d \$f4,\$f6
[0-9a-f]+ <[^>]*> c.f.d \$fcc1,\$f4,\$f6
[0-9a-f]+ <[^>]*> ldxc1 \$f2,a0\(a1\)
diff --git a/gas/testsuite/gas/mips/mips4-fp.l b/gas/testsuite/gas/mips/mips4-fp.l
index 2013256b3f8..908e29f77d3 100644
--- a/gas/testsuite/gas/mips/mips4-fp.l
+++ b/gas/testsuite/gas/mips/mips4-fp.l
@@ -1,35 +1,33 @@
.*: Assembler messages:
.*:4: Error: opcode not supported on this processor: .* \(.*\) `bc1f text_label'
.*:5: Error: opcode not supported on this processor: .* \(.*\) `bc1f \$fcc1,text_label'
-.*:6: Error: opcode not supported on this processor: .* \(.*\) `bc1fl \$fcc1,text_label'
-.*:7: Error: opcode not supported on this processor: .* \(.*\) `bc1t \$fcc1,text_label'
-.*:8: Error: opcode not supported on this processor: .* \(.*\) `bc1tl \$fcc2,text_label'
-.*:9: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$f4,\$f6'
-.*:10: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$fcc1,\$f4,\$f6'
-.*:11: Error: opcode not supported on this processor: .* \(.*\) `ldxc1 \$f2,\$4\(\$5\)'
-.*:12: Error: opcode not supported on this processor: .* \(.*\) `lwxc1 \$f2,\$4\(\$5\)'
-.*:13: Error: opcode not supported on this processor: .* \(.*\) `madd.d \$f0,\$f2,\$f4,\$f6'
-.*:15: Error: opcode not supported on this processor: .* \(.*\) `madd.s \$f10,\$f8,\$f2,\$f0'
-.*:16: Error: opcode not supported on this processor: .* \(.*\) `movf \$4,\$5,\$fcc4'
-.*:17: Error: opcode not supported on this processor: .* \(.*\) `movf.d \$f4,\$f6,\$fcc0'
-.*:18: Error: opcode not supported on this processor: .* \(.*\) `movf.s \$f4,\$f6,\$fcc0'
-.*:19: Error: opcode not supported on this processor: .* \(.*\) `movn.d \$f4,\$f6,\$6'
-.*:20: Error: opcode not supported on this processor: .* \(.*\) `movn.s \$f4,\$f6,\$6'
-.*:21: Error: opcode not supported on this processor: .* \(.*\) `movt \$4,\$5,\$fcc4'
-.*:22: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f4,\$f6,\$fcc0'
-.*:23: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f4,\$f6,\$fcc0'
-.*:24: Error: opcode not supported on this processor: .* \(.*\) `movz.d \$f4,\$f6,\$6'
-.*:25: Error: opcode not supported on this processor: .* \(.*\) `movz.s \$f4,\$f6,\$6'
-.*:26: Error: opcode not supported on this processor: .* \(.*\) `msub.d \$f0,\$f2,\$f4,\$f6'
-.*:27: Error: opcode not supported on this processor: .* \(.*\) `msub.s \$f0,\$f2,\$f4,\$f6'
-.*:28: Error: opcode not supported on this processor: .* \(.*\) `nmadd.d \$f0,\$f2,\$f4,\$f6'
-.*:29: Error: opcode not supported on this processor: .* \(.*\) `nmadd.s \$f0,\$f2,\$f4,\$f6'
-.*:30: Error: opcode not supported on this processor: .* \(.*\) `nmsub.d \$f0,\$f2,\$f4,\$f6'
-.*:31: Error: opcode not supported on this processor: .* \(.*\) `nmsub.s \$f0,\$f2,\$f4,\$f6'
-.*:33: Error: opcode not supported on this processor: .* \(.*\) `prefx 4,\$4\(\$5\)'
-.*:34: Error: opcode not supported on this processor: .* \(.*\) `recip.d \$f4,\$f6'
-.*:35: Error: opcode not supported on this processor: .* \(.*\) `recip.s \$f4,\$f6'
-.*:36: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.d \$f4,\$f6'
-.*:37: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.s \$f4,\$f6'
-.*:38: Error: opcode not supported on this processor: .* \(.*\) `sdxc1 \$f4,\$4\(\$5\)'
-.*:39: Error: opcode not supported on this processor: .* \(.*\) `swxc1 \$f4,\$4\(\$5\)'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `bc1t \$fcc1,text_label'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$f4,\$f6'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$fcc1,\$f4,\$f6'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `ldxc1 \$f2,\$4\(\$5\)'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `lwxc1 \$f2,\$4\(\$5\)'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `madd.d \$f0,\$f2,\$f4,\$f6'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `madd.s \$f10,\$f8,\$f2,\$f0'
+.*:14: Error: opcode not supported on this processor: .* \(.*\) `movf \$4,\$5,\$fcc4'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `movf.d \$f4,\$f6,\$fcc0'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `movf.s \$f4,\$f6,\$fcc0'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `movn.d \$f4,\$f6,\$6'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `movn.s \$f4,\$f6,\$6'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `movt \$4,\$5,\$fcc4'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f4,\$f6,\$fcc0'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f4,\$f6,\$fcc0'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `movz.d \$f4,\$f6,\$6'
+.*:23: Error: opcode not supported on this processor: .* \(.*\) `movz.s \$f4,\$f6,\$6'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `msub.d \$f0,\$f2,\$f4,\$f6'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `msub.s \$f0,\$f2,\$f4,\$f6'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `nmadd.d \$f0,\$f2,\$f4,\$f6'
+.*:27: Error: opcode not supported on this processor: .* \(.*\) `nmadd.s \$f0,\$f2,\$f4,\$f6'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `nmsub.d \$f0,\$f2,\$f4,\$f6'
+.*:29: Error: opcode not supported on this processor: .* \(.*\) `nmsub.s \$f0,\$f2,\$f4,\$f6'
+.*:31: Error: opcode not supported on this processor: .* \(.*\) `prefx 4,\$4\(\$5\)'
+.*:32: Error: opcode not supported on this processor: .* \(.*\) `recip.d \$f4,\$f6'
+.*:33: Error: opcode not supported on this processor: .* \(.*\) `recip.s \$f4,\$f6'
+.*:34: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.d \$f4,\$f6'
+.*:35: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.s \$f4,\$f6'
+.*:36: Error: opcode not supported on this processor: .* \(.*\) `sdxc1 \$f4,\$4\(\$5\)'
+.*:37: Error: opcode not supported on this processor: .* \(.*\) `swxc1 \$f4,\$4\(\$5\)'
diff --git a/gas/testsuite/gas/mips/mips4-fp.s b/gas/testsuite/gas/mips/mips4-fp.s
index d181e684feb..5d28aeabd6d 100644
--- a/gas/testsuite/gas/mips/mips4-fp.s
+++ b/gas/testsuite/gas/mips/mips4-fp.s
@@ -3,9 +3,7 @@
text_label:
bc1f text_label
bc1f $fcc1,text_label
- bc1fl $fcc1,text_label
bc1t $fcc1,text_label
- bc1tl $fcc2,text_label
c.f.d $f4,$f6
c.f.d $fcc1,$f4,$f6
ldxc1 $f2,$4($5)