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Remove, rename using dos-compatible 8.3 names.

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This commit is contained in:
Michael Snyder
2003-05-14 20:01:55 +00:00
parent 85e851634c
commit ab12e95ba6
21 changed files with 0 additions and 11266 deletions

778
sim/testsuite/sim/h8300/add.b.s

@ -1,778 +0,0 @@
# Hitachi H8 testcase 'add.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# add.b #xx:8, rd ; 8 rd xxxxxxxx
# add.b #xx:8, @erd ; 7 d rd ???? 8 ???? xxxxxxxx
# add.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? 8 ???? xxxxxxxx
# add.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? 8 ???? xxxxxxxx
# add.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? 8 ???? xxxxxxxx
# add.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? 8 ???? xxxxxxxx
# add.b #xx:8, @(d:16, erd) ; 0 1 7 4 6 e b30 | rd, b31, dd:16 8 ???? xxxxxxxx
# add.b #xx:8, @(d:32, erd) ; 7 8 b30 | rd, 4 6 a 2 8 dd:32 8 ???? xxxxxxxx
# add.b #xx:8, @aa:8 ; 7 f aaaaaaaa 8 ???? xxxxxxxx
# add.b #xx:8, @aa:16 ; 6 a 1 1??? aa:16 8 ???? xxxxxxxx
# add.b #xx:8, @aa:32 ; 6 a 3 1??? aa:32 8 ???? xxxxxxxx
# add.b rs, rd ; 0 8 rs rd
# add.b reg8, @erd ; 7 d rd ???? 0 8 rs ????
# add.b reg8, @erd+ ; 0 1 7 9 8 rd 1 rs
# add.b reg8, @erd- ; 0 1 7 9 a rd 1 rs
# add.b reg8, @+erd ; 0 1 7 9 9 rd 1 rs
# add.b reg8, @-erd ; 0 1 7 9 b rd 1 rs
# add.b reg8, @(d:16, erd) ; 0 1 7 9 c b30 | rd32, 1 rs8 imm16
# add.b reg8, @(d:32, erd) ; 0 1 7 9 d b31 | rd32, 1 rs8 imm32
# add.b reg8, @aa:8 ; 7 f aaaaaaaa 0 8 rs ????
# add.b reg8, @aa:16 ; 6 a 1 1??? aa:16 0 8 rs ????
# add.b reg8, @aa:32 ; 6 a 3 1??? aa:32 0 8 rs ????
#
# Coming soon:
# add.b #xx:8, @(d:2, erd) ; 0 1 7 b30 | b21 | dd:2, 8 ???? xxxxxxxx
# add.b reg8, @(d:2, erd) ; 0 1 7 9 dd:2 rd32 1 rs8
# ...
.data
pre_byte: .byte 0
byte_dest: .byte 0
post_byte: .byte 0
start
add_b_imm8_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; add.b #xx:8,Rd
add.b #5:8, r0l ; Immediate 8-bit src, reg8 dst
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5aa r0 ; add result: a5 + 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
add_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@eRd
mov #byte_dest, er0
add.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst
;;; .word 0x7d00
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest, er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #5, r0l
beq .L1
fail
.L1:
add_b_imm8_rdpostinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@eRd+
mov #byte_dest, er0
add.b #5:8, @er0+ ; Immediate 8-bit src, reg post-inc dst
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte, er0 ; er0 contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #10, r0l
beq .L2
fail
.L2:
add_b_imm8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@eRd-
mov #byte_dest, er0
add.b #5:8, @er0- ; Immediate 8-bit src, reg post-dec dst
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte, er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #15, r0l
beq .L3
fail
.L3:
add_b_imm8_rdpreinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@+eRd
mov #pre_byte, er0
add.b #5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #20, r0l
beq .L4
fail
.L4:
add_b_imm8_rdpredec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@-eRd
mov #post_byte, er0
add.b #5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #25, r0l
beq .L5
fail
.L5:
add_b_imm8_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@(dd:16, eRd)
mov #post_byte, er0
add.b #5:8, @(-1:16, er0) ; Immediate 8-bit src, 16-bit reg disp dest.
;;; .word 0x0174
;;; .word 0x6e08
;;; .word 0xffff
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte, er0 ; er0 contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #30, r0l
beq .L6
fail
.L6:
add_b_imm8_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@(dd:32, eRd)
mov #pre_byte, er0
add.b #5:8, @(1:32, er0) ; Immediate 8-bit src, 32-bit reg disp. dest.
;;; .word 0x7804
;;; .word 0x6a28
;;; .word 0x0000
;;; .word 0x0001
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte, er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #35, r0l
beq .L7
fail
.L7:
add_b_imm8_abs8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b reg8,@aa:8
;; NOTE: for abs8, we will use the SBR register as a base,
;; since otherwise we would have to make sure that the destination
;; was in the zero page.
;;
mov #byte_dest-100, er0
ldc er0, sbr
add.b #5, @100:8 ; 8-bit reg src, 8-bit absolute dest
;;; .word 0x7f64
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest-100, er0 ; reg 0 has base address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #40, r0l
beq .L8
fail
.L8:
add_b_imm8_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@aa:16
add.b #5:8, @byte_dest:16 ; Immediate 8-bit src, 16-bit absolute dest
;;; .word 0x6a18
;;; .word byte_dest
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #45, r0l
beq .L9
fail
.L9:
add_b_imm8_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@aa:32
add.b #5:8, @byte_dest:32 ; Immediate 8-bit src, 32-bit absolute dest
;;; .word 0x6a38
;;; .long byte_dest
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #50, r0l
beq .L10
fail
.L10:
.endif
add_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; add.b Rs,Rd
mov.b #5, r0h
add.b r0h, r0l ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x05aa r0 ; add result: a5 + 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
add_b_reg8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b rs8,@eRd ; Add to register indirect
mov #byte_dest, er0
mov #5, r1l
add.b r1l, @er0 ; reg8 src, reg indirect dest
;;; .word 0x7d00
;;; .word 0x0890
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #55, r0l
beq .L11
fail
.L11:
add_b_reg8_rdpostinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b rs8,@eRd+ ; Add to register post-increment
mov #byte_dest, er0
mov #5, r1l
add.b r1l, @er0+ ; reg8 src, reg post-incr dest
;;; .word 0x0179
;;; .word 0x8019
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #60, r0l
beq .L12
fail
.L12:
add_b_reg8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b rs8,@eRd- ; Add to register post-decrement
mov #byte_dest, er0
mov #5, r1l
add.b r1l, @er0- ; reg8 src, reg post-decr dest
;;; .word 0x0179
;;; .word 0xa019
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #65, r0l
beq .L13
fail
.L13:
add_b_reg8_rdpreinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b rs8,@+eRd ; Add to register pre-increment
mov #pre_byte, er0
mov #5, r1l
add.b r1l, @+er0 ; reg8 src, reg pre-incr dest
;;; .word 0x0179
;;; .word 0x9019
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #70, r0l
beq .L14
fail
.L14:
add_b_reg8_rdpredec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b rs8,@-eRd ; Add to register pre-decrement
mov #post_byte, er0
mov #5, r1l
add.b r1l, @-er0 ; reg8 src, reg pre-decr dest
;;; .word 0x0179
;;; .word 0xb019
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #75, r0l
beq .L15
fail
.L15:
add_b_reg8_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b rs8,@(dd:16, eRd) ; Add to register + 16-bit displacement
mov #pre_byte, er0
mov #5, r1l
add.b r1l, @(1:16, er0) ; reg8 src, 16-bit reg disp dest
;;; .word 0x0179
;;; .word 0xc019
;;; .word 0x0001
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #80, r0l
beq .L16
fail
.L16:
add_b_reg8_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b rs8,@-eRd ; Add to register plus 32-bit displacement
mov #post_byte, er0
mov #5, r1l
add.b r1l, @(-1:32, er0) ; reg8 src, 32-bit reg disp dest
;;; .word 0x0179
;;; .word 0xd819
;;; .word 0xffff
;;; .word 0xffff
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #85, r0l
beq .L17
fail
.L17:
add_b_reg8_abs8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b reg8,@aa:8
;; NOTE: for abs8, we will use the SBR register as a base,
;; since otherwise we would have to make sure that the destination
;; was in the zero page.
;;
mov #byte_dest-100, er0
ldc er0, sbr
mov #5, r1l
add.b r1l, @100:8 ; 8-bit reg src, 8-bit absolute dest
;;; .word 0x7f64
;;; .word 0x0890
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest-100, er0 ; reg 0 has base address
test_h_gr32 0xa5a5a505 er1 ; reg 1 has test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #90, r0l
beq .L18
fail
.L18:
add_b_reg8_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b reg8,@aa:16
mov #5, r0l
add.b r0l, @byte_dest:16 ; 8-bit reg src, 16-bit absolute dest
;;; .word 0x6a18
;;; .word byte_dest
;;; .word 0x0880
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #95, r0l
beq .L19
fail
.L19:
add_b_reg8_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b reg8,@aa:32
mov #5, r0l
add.b r0l, @byte_dest:32 ; 8-bit reg src, 32-bit absolute dest
;;; .word 0x6a38
;;; .long byte_dest
;;; .word 0x0880
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #100, r0l
beq .L20
fail
.L20:
.endif
pass
exit 0

1865
sim/testsuite/sim/h8300/add.l.s

File diff suppressed because it is too large Load Diff

87
sim/testsuite/sim/h8300/add.w.s

@ -1,87 +0,0 @@
# Hitachi H8 testcase 'add.w'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# add.w xx:3, rd ; 0 a 0xxx rd (sx only)
# add.w xx:16, rd ; 7 9 1 rd imm16
# add.w rs, rd ; 0 9 rs rd
#
start
.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
add_w_imm3:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; add.w #xx:3,Rd ; Immediate 3-bit operand
add.w #7, r0 ; FIXME will not assemble yet
; .word 0x0a70 ; Fake it until assembler will take it.
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5ac r0 ; add result: a5a5 + 7
test_h_gr32 0xa5a5a5ac er0 ; add result: a5a5 + 7
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu) ; non-zero means h8300h, s, or sx
add_w_imm16:
;; add.w immediate not available in h8300 mode.
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; add.w #xx:16,Rd
add.w #0x111, r0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111
test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
add_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; add.w Rs,Rd
mov.w #0x111, r1
add.w r1, r0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111
test_h_gr16 0x0111 r1
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111
test_h_gr32 0xa5a50111 er1
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

491
sim/testsuite/sim/h8300/and.b.s

@ -1,491 +0,0 @@
# Hitachi H8 testcase 'and.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# and.b #xx:8, rd ; e rd xxxxxxxx
# and.b #xx:8, @erd ; 7 d rd ???? e ???? xxxxxxxx
# and.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx
# and.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx
# and.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx
# and.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx
# and.b rs, rd ; 1 6 rs rd
# and.b reg8, @erd ; 7 d rd ???? 1 6 rs ????
# and.b reg8, @erd+ ; 0 1 7 9 8 rd 6 rs
# and.b reg8, @erd- ; 0 1 7 9 a rd 6 rs
# and.b reg8, @+erd ; 0 1 7 9 9 rd 6 rs
# and.b reg8, @-erd ; 0 1 7 9 b rd 6 rs
#
# andc #xx:8, ccr ; 0 6 xxxxxxxx
# andc #xx:8, exr ; 0 1 4 1 0 6 xxxxxxxx
# Coming soon:
# ...
.data
pre_byte: .byte 0
byte_dest: .byte 0xa5
post_byte: .byte 0
start
and_b_imm8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.b #xx:8,Rd
and.b #0xaa, r0l ; Immediate 8-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a0 r0 ; and result: a5 & aa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a0 er0 ; and result: a5 & aa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
and_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@eRd
mov #byte_dest, er0
and.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst
;;; .word 0x7d00
;;; .word 0xe0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L1
fail
.L1:
and_b_imm8_rdpostinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@eRd+
mov #byte_dest, er0
and.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xe055
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte, er0 ; er0 contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L2
fail
.L2:
and_b_imm8_rdpostdec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@eRd-
mov #byte_dest, er0
and.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xe0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte, er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L3
fail
.L3:
and_b_imm8_rdpreinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@+eRd
mov #pre_byte, er0
and.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0xe055
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L4
fail
.L4:
and_b_imm8_rdpredec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@-eRd
mov #post_byte, er0
and.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0xe0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L5
fail
.L5:
.endif
and_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.b Rs,Rd
mov.b #0xaa, r0h
and.b r0h, r0l ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xaaa0 r0 ; and result: a5 & aa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5aaa0 er0 ; and result: a5 & aa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
and_b_reg8_rdind:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@eRd ; And to register indirect
mov #byte_dest, er0
mov #0x55, r1l
and.b r1l, @er0 ; reg8 src, reg indirect dest
;;; .word 0x7d00
;;; .word 0x1690
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L6
fail
.L6:
and_b_reg8_rdpostinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@eRd+ ; And to register post-incr
mov #byte_dest, er0
mov #0xaa, r1l
and.b r1l, @er0+ ; reg8 src, reg post-incr dest
;;; .word 0x0179
;;; .word 0x8069
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L7
fail
.L7:
and_b_reg8_rdpostdec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@eRd- ; And to register post-decr
mov #byte_dest, er0
mov #0x55, r1l
and.b r1l, @er0- ; reg8 src, reg post-decr dest
;;; .word 0x0179
;;; .word 0xa069
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L8
fail
.L8:
and_b_reg8_rdpreinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@+eRd ; And to register post-incr
mov #pre_byte, er0
mov #0xaa, r1l
and.b r1l, @+er0 ; reg8 src, reg post-incr dest
;;; .word 0x0179
;;; .word 0x9069
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L9
fail
.L9:
and_b_reg8_rdpredec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@-eRd ; And to register post-decr
mov #post_byte, er0
mov #0x55, r1l
and.b r1l, @-er0 ; reg8 src, reg post-decr dest
;;; .word 0x0179
;;; .word 0xb069
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L10
fail
.L10:
andc_imm8_ccr:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; andc #xx:8,ccr
set_ccr 0xff
test_neg_set
andc #0xf7, ccr ; Immediate 8-bit operand (neg flag)
test_neg_clear
test_zero_set
andc #0xfb, ccr ; Immediate 8-bit operand (zero flag)
test_zero_clear
test_ovf_set
andc #0xfd, ccr ; Immediate 8-bit operand (overflow flag)
test_ovf_clear
test_carry_set
andc #0xfe, ccr ; Immediate 8-bit operand (carry flag)
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0

77
sim/testsuite/sim/h8300/and.l.s

@ -1,77 +0,0 @@
# Hitachi H8 testcase 'and.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx.
and_l_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.l #xx:16,Rd
and.l #0xaaaa:16, er0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x0000a0a0 er0 ; and result: a5a5a5a5 & aaaa
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
and_l_imm32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.l #xx:32,Rd
and.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
and_l_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.l Rs,Rd
mov.l #0xaaaaaaaa, er1
and.l er1, er0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa
test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

61
sim/testsuite/sim/h8300/and.w.s

@ -1,61 +0,0 @@
# Hitachi H8 testcase 'and.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu) ; non-zero means h8300h, s, or sx
and_w_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.w #xx:16,Rd
and.w #0xaaaa, r0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
and_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.w Rs,Rd
mov.w #0xaaaa, r1
and.w r1, r0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa
test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa
test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

625
sim/testsuite/sim/h8300/cmp.b.s

@ -1,625 +0,0 @@
# Hitachi H8 testcase 'cmp.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# cmp.b #xx:8, rd ; a rd xxxxxxxx
# cmp.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx
# cmp.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx
# cmp.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx
# cmp.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx
# cmp.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx
# cmp.b rs, rd ; 1 c rs rd
# cmp.b reg8, @erd ; 7 d rd ???? 1 c rs ????
# cmp.b reg8, @erd+ ; 0 1 7 9 8 rd 2 rs
# cmp.b reg8, @erd- ; 0 1 7 9 a rd 2 rs
# cmp.b reg8, @+erd ; 0 1 7 9 9 rd 2 rs
# cmp.b reg8, @-erd ; 0 1 7 9 b rd 2 rs
#
# Coming soon:
# ...
.data
pre_byte: .byte 0
byte_dest: .byte 0xa5
post_byte: .byte 0
start
cmp_b_imm8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.b #xx:8,Rd
cmp.b #0xa5, r0l ; Immediate 8-bit src, reg8 dest
beq .Leq1
fail
.Leq1: cmp.b #0xa6, r0l
blt .Llt1
fail
.Llt1: cmp.b #0xa4, r0l
bgt .Lgt1
fail
.Lgt1:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a5 r0 ; r0 unchanged
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
cmp_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b #xx:8,@eRd
mov #byte_dest, er0
cmp.b #0xa5:8, @er0 ; Immediate 8-bit src, reg indirect dst
;;; .word 0x7d00
;;; .word 0xa0a5
beq .Leq2
fail
.Leq2: set_ccr_zero
cmp.b #0xa6, @er0
;;; .word 0x7d00
;;; .word 0xa0a6
blt .Llt2
fail
.Llt2: set_ccr_zero
cmp.b #0xa4, @er0
;;; .word 0x7d00
;;; .word 0xa0a4
bgt .Lgt2
fail
.Lgt2:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L2
fail
.L2:
cmp_b_imm8_rdpostinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b #xx:8,@eRd+
mov #byte_dest, er0
cmp.b #0xa5:8, @er0+ ; Immediate 8-bit src, reg postinc dst
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xa0a5
beq .Leq3
fail
.Leq3: test_h_gr32 post_byte er0 ; er0 contains address plus one
mov #byte_dest, er0
set_ccr_zero
cmp.b #0xa6, @er0+
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xa0a6
blt .Llt3
fail
.Llt3: test_h_gr32 post_byte er0 ; er0 contains address plus one
mov #byte_dest, er0
set_ccr_zero
cmp.b #0xa4, @er0+
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xa0a4
bgt .Lgt3
fail
.Lgt3:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L3
fail
.L3:
cmp_b_imm8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b #xx:8,@eRd-
mov #byte_dest, er0
cmp.b #0xa5:8, @er0- ; Immediate 8-bit src, reg postdec dst
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xa0a5
beq .Leq4
fail
.Leq4: test_h_gr32 pre_byte er0 ; er0 contains address minus one
mov #byte_dest, er0
set_ccr_zero
cmp.b #0xa6, @er0-
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xa0a6
blt .Llt4
fail
.Llt4: test_h_gr32 pre_byte er0 ; er0 contains address minus one
mov #byte_dest, er0
set_ccr_zero
cmp.b #0xa4, @er0-
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xa0a4
bgt .Lgt4
fail
.Lgt4:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L4
fail
.L4:
cmp_b_imm8_rdpreinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b #xx:8,@+eRd
mov #pre_byte, er0
cmp.b #0xa5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0xa0a5
beq .Leq5
fail
.Leq5: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #pre_byte, er0
set_ccr_zero
cmp.b #0xa6, @+er0
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0xa0a6
blt .Llt5
fail
.Llt5: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #pre_byte, er0
set_ccr_zero
cmp.b #0xa4, @+er0
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0xa0a4
bgt .Lgt5
fail
.Lgt5:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L5
fail
.L5:
cmp_b_imm8_rdpredec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b #xx:8,@-eRd
mov #post_byte, er0
cmp.b #0xa5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0xa0a5
beq .Leq6
fail
.Leq6: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #post_byte, er0
set_ccr_zero
cmp.b #0xa6, @-er0
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0xa0a6
blt .Llt6
fail
.Llt6: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #post_byte, er0
set_ccr_zero
cmp.b #0xa4, @-er0
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0xa0a4
bgt .Lgt6
fail
.Lgt6:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L6
fail
.L6:
.endif
cmp_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.b Rs,Rd
mov.b #0xa5, r0h
cmp.b r0h, r0l ; Reg8 src, reg8 dst
beq .Leq7
fail
.Leq7: mov.b #0xa6, r0h
cmp.b r0h, r0l
blt .Llt7
fail
.Llt7: mov.b #0xa4, r0h
cmp.b r0h, r0l
bgt .Lgt7
fail
.Lgt7:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa4a5 r0 ; r0l unchanged.
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a4a5 er0 ; r0l unchanged
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
cmp_b_reg8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b rs8,@eRd ; cmp reg8 to register indirect
mov #byte_dest, er0
mov #0xa5, r1l
cmp.b r1l, @er0 ; reg8 src, reg indirect dest
;;; .word 0x7d00
;;; .word 0x1c90
beq .Leq8
fail
.Leq8: set_ccr_zero
mov #0xa6, r1l
cmp.b r1l, @er0
;;; .word 0x7d00
;;; .word 0x1c90
blt .Llt8
fail
.Llt8: set_ccr_zero
mov #0xa4, r1l
cmp.b r1l, @er0
;;; .word 0x7d00
;;; .word 0x1c90
bgt .Lgt8
fail
.Lgt8:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a5a4 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (no change).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L8
fail
.L8:
cmp_b_reg8_rdpostinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b reg8,@eRd+
mov #byte_dest, er0
mov #0xa5, r1l
cmp.b r1l, @er0+ ; Immediate 8-bit src, reg post-incr dst
;;; .word 0x0179
;;; .word 0x8029
beq .Leq9
fail
.Leq9: test_h_gr32 post_byte er0 ; er0 contains address plus one
mov #byte_dest er0
mov #0xa6, r1l
set_ccr_zero
cmp.b r1l, @er0+
;;; .word 0x0179
;;; .word 0x8029
blt .Llt9
fail
.Llt9: test_h_gr32 post_byte er0 ; er0 contains address plus one
mov #byte_dest er0
mov #0xa4, r1l
set_ccr_zero
cmp.b r1l, @er0+
;;; .word 0x0179
;;; .word 0x8029
bgt .Lgt9
fail
.Lgt9:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L9
fail
.L9:
cmp_b_reg8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b reg8,@eRd-
mov #byte_dest, er0
mov #0xa5, r1l
cmp.b r1l, @er0- ; Immediate 8-bit src, reg postdec dst
;;; .word 0x0179
;;; .word 0xa029
beq .Leq10
fail
.Leq10: test_h_gr32 pre_byte er0 ; er0 contains address minus one
mov #byte_dest er0
mov #0xa6, r1l
set_ccr_zero
cmp.b r1l, @er0-
;;; .word 0x0179
;;; .word 0xa029
blt .Llt10
fail
.Llt10: test_h_gr32 pre_byte er0 ; er0 contains address minus one
mov #byte_dest er0
mov #0xa4, r1l
set_ccr_zero
cmp.b r1l, @er0-
;;; .word 0x0179
;;; .word 0xa029
bgt .Lgt10
fail
.Lgt10:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L10
fail
.L10:
cmp_b_reg8_rdpreinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b reg8,@+eRd
mov #pre_byte, er0
mov #0xa5, r1l
cmp.b r1l, @+er0 ; Immediate 8-bit src, reg post-incr dst
;;; .word 0x0179
;;; .word 0x9029
beq .Leq11
fail
.Leq11: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #pre_byte er0
mov #0xa6, r1l
set_ccr_zero
cmp.b r1l, @+er0
;;; .word 0x0179
;;; .word 0x9029
blt .Llt11
fail
.Llt11: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #pre_byte er0
mov #0xa4, r1l
set_ccr_zero
cmp.b r1l, @+er0
;;; .word 0x0179
;;; .word 0x9029
bgt .Lgt11
fail
.Lgt11:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L11
fail
.L11:
cmp_b_reg8_rdpredec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b reg8,@-eRd
mov #post_byte, er0
mov #0xa5, r1l
cmp.b r1l, @-er0 ; Immediate 8-bit src, reg postdec dst
;;; .word 0x0179
;;; .word 0xb029
beq .Leq12
fail
.Leq12: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #post_byte er0
mov #0xa6, r1l
set_ccr_zero
cmp.b r1l, @-er0
;;; .word 0x0179
;;; .word 0xb029
blt .Llt12
fail
.Llt12: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #post_byte er0
mov #0xa4, r1l
set_ccr_zero
cmp.b r1l, @-er0
;;; .word 0x0179
;;; .word 0xb029
bgt .Lgt12
fail
.Lgt12:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L12
fail
.L12:
.endif
pass
exit 0

106
sim/testsuite/sim/h8300/cmp.l.s

@ -1,106 +0,0 @@
# Hitachi H8 testcase 'cmp.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
cmp_l_imm3: ;
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.l #xx:3,eRd ; Immediate 3-bit operand
mov.l #5, er0
cmp.l #5, er0
beq eq3
fail
eq3:
cmp.l #6, er0
blt lt3
fail
lt3:
cmp.l #4, er0
bgt gt3
fail
gt3:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x00000005 er0 ; er0 unchanged
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
cmp_l_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.l #xx:8,Rd
cmp.l #0xa5a5a5a5, er0 ; Immediate 16-bit operand
beq eqi
fail
eqi: cmp.l #0xa5a5a5a6, er0
blt lti
fail
lti: cmp.l #0xa5a5a5a4, er0
bgt gti
fail
gti:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.l Rs,Rd
mov.l #0xa5a5a5a5, er1
cmp.l er1, er0 ; Register operand
beq eqr
fail
eqr: mov.l #0xa5a5a5a6, er1
cmp.l er1, er0
blt ltr
fail
ltr: mov.l #0xa5a5a5a4, er1
cmp.l er1, er0
bgt gtr
fail
gtr:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged
test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

110
sim/testsuite/sim/h8300/cmp.w.s

@ -1,110 +0,0 @@
# Hitachi H8 testcase 'cmp.w'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
cmp_w_imm3: ;
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.w #xx:3,Rd ; Immediate 3-bit operand
mov.w #5, r0
cmp.w #5, r0
beq eq3
fail
eq3:
cmp.w #6, r0
blt lt3
fail
lt3:
cmp.w #4, r0
bgt gt3
fail
gt3:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a50005 er0 ; er0 unchanged
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu) ; non-zero means h8300h, s, or sx
cmp_w_imm16: ; cmp.w immediate not available in h8300 mode.
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.w #xx:8,Rd
cmp.w #0xa5a5, r0 ; Immediate 16-bit operand
beq eqi
fail
eqi: cmp.w #0xa5a6, r0
blt lti
fail
lti: cmp.w #0xa5a4, r0
bgt gti
fail
gti:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a5 r0 ; r0 unchanged
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
cmp_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.w Rs,Rd
mov.w #0xa5a5, r1
cmp.w r1, r0 ; Register operand
beq eqr
fail
eqr: mov.w #0xa5a6, r1
cmp.w r1, r0
blt ltr
fail
ltr: mov.w #0xa5a4, r1
cmp.w r1, r0
bgt gtr
fail
gtr:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a5 r0 ; r0 unchanged.
test_h_gr16 0xa5a4 r1 ; r1 unchanged.
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged
test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

1495
sim/testsuite/sim/h8300/mov.b.s

File diff suppressed because it is too large Load Diff

2160
sim/testsuite/sim/h8300/mov.l.s

File diff suppressed because it is too large Load Diff

1857
sim/testsuite/sim/h8300/mov.w.s

File diff suppressed because it is too large Load Diff

493
sim/testsuite/sim/h8300/or.b.s

@ -1,493 +0,0 @@
# Hitachi H8 testcase 'or.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# or.b #xx:8, rd ; c rd xxxxxxxx
# or.b #xx:8, @erd ; 7 d rd ???? c ???? xxxxxxxx
# or.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? c ???? xxxxxxxx
# or.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? c ???? xxxxxxxx
# or.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? c ???? xxxxxxxx
# or.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? c ???? xxxxxxxx
# or.b rs, rd ; 1 4 rs rd
# or.b reg8, @erd ; 7 d rd ???? 1 4 rs ????
# or.b reg8, @erd+ ; 0 1 7 9 8 rd 4 rs
# or.b reg8, @erd- ; 0 1 7 9 a rd 4 rs
# or.b reg8, @+erd ; 0 1 7 9 9 rd 4 rs
# or.b reg8, @-erd ; 0 1 7 9 b rd 4 rs
#
# Coming soon:
# ...
.data
pre_byte: .byte 0
byte_dest: .byte 0xa5
post_byte: .byte 0
start
or_b_imm8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.b #xx:8,Rd
or.b #0xaa, r0l ; Immediate 8-bit src, reg8 dest
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5af r0 ; or result: a5 | aa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5af er0 ; or result: a5 | aa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
or_b_imm8_rdind:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@eRd
mov #byte_dest, er0
or.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst
;;; .word 0x7d00
;;; .word 0xc0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L1
fail
.L1:
or_b_imm8_rdpostinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@eRd+
mov #byte_dest, er0
or.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xc055
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte, er0 ; er0 contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xf5, r0l
beq .L2
fail
.L2:
or_b_imm8_rdpostdec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@eRd-
mov #byte_dest, er0
or.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xc0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte, er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L3
fail
.L3:
or_b_imm8_rdpreinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@+eRd
mov #pre_byte, er0
or.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0xc055
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xf5, r0l
beq .L4
fail
.L4:
or_b_imm8_rdpredec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@-eRd
mov #post_byte, er0
or.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0xc0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L5
fail
.L5:
.endif
or_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.b Rs,Rd
mov.b #0xaa, r0h
or.b r0h, r0l ; Reg8 src, reg8 dest
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xaaaf r0 ; or result: a5 | aa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5aaaf er0 ; or result: a5 | aa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
or_b_reg8_rdind:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@eRd ; or reg8 to register indirect
mov #byte_dest, er0
mov #0xaa, r1l
or.b r1l, @er0 ; reg8 src, reg indirect dest
;;; .word 0x7d00
;;; .word 0x1490
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L6
fail
.L6:
or_b_reg8_rdpostinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@eRd+ ; or reg8 to register indirect post-increment
mov #byte_dest, er0
mov #0x55, r1l
or.b r1l, @er0+ ; reg8 src, reg post-incr dest
;;; .word 0x0179
;;; .word 0x8049
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xf5, r0l
beq .L7
fail
.L7:
or_b_reg8_rdpostdec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@eRd- ; or reg8 to register indirect post-decrement
mov #byte_dest, er0
mov #0xaa, r1l
or.b r1l, @er0- ; reg8 src, reg post-decr dest
;;; .word 0x0179
;;; .word 0xa049
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L8
fail
.L8:
or_b_reg8_rdpreinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@+eRd ; or reg8 to register indirect pre-increment
mov #pre_byte, er0
mov #0x55, r1l
or.b r1l, @+er0 ; reg8 src, reg pre-incr dest
;;; .word 0x0179
;;; .word 0x9049
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xf5, r0l
beq .L9
fail
.L9:
or_b_reg8_rdpredec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@-eRd ; or reg8 to register indirect pre-decrement
mov #post_byte, er0
mov #0xaa, r1l
or.b r1l, @-er0 ; reg8 src, reg pre-decr dest
;;; .word 0x0179
;;; .word 0xb049
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L10
fail
.L10:
orc_imm8_ccr:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; orc #xx:8,ccr
test_neg_clear
orc #0x8, ccr ; Immediate 8-bit operand (neg flag)
test_neg_set
test_zero_clear
orc #0x4, ccr ; Immediate 8-bit operand (zero flag)
test_zero_set
test_ovf_clear
orc #0x2, ccr ; Immediate 8-bit operand (overflow flag)
test_ovf_set
test_carry_clear
orc #0x1, ccr ; Immediate 8-bit operand (carry flag)
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0

77
sim/testsuite/sim/h8300/or.l.s

@ -1,77 +0,0 @@
# Hitachi H8 testcase 'or.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx.
or_l_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.l #xx:16,Rd
or.l #0xaaaa, er0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5afaf er0 ; or result: a5a5a5a5 | aaaa
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
or_l_imm32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.l #xx:32,Rd
or.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
or_l_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.l Rs,Rd
mov.l #0xaaaaaaaa, er1
or.l er1, er0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa
test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

61
sim/testsuite/sim/h8300/or.w.s

@ -1,61 +0,0 @@
# Hitachi H8 testcase 'or.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu) ; non-zero means h8300h, s, or sx
or_w_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.w #xx:16,Rd
or.w #0xaaaa, r0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
or_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.w Rs,Rd
mov.w #0xaaaa, r1
or.w r1, r0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa
test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa
test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

289
sim/testsuite/sim/h8300/sub.b.s

@ -1,289 +0,0 @@
# Hitachi H8 testcase 'sub.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# sub.b #xx:8, rd ; <illegal>
# sub.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx
# sub.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx
# sub.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx
# sub.b rs, rd ; 1 8 rs rd
# sub.b reg8, @erd ; 7 d rd ???? 1 8 rs ????
# sub.b reg8, @erd+ ; 0 1 7 9 8 rd 3 rs
# sub.b reg8, @erd- ; 0 1 7 9 a rd 3 rs
#
# Coming soon:
# sub.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx
# sub.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx
# sub.b reg8, @+erd ; 0 1 7 9 9 rd 3 rs
# sub.b reg8, @-erd ; 0 1 7 9 b rd 3 rs
# ...
.data
pre_byte: .byte 0
byte_dest: .byte 0xa5
post_byte: .byte 0
start
.if (0) ; Guess what? Sub.b immediate reg8 is illegal!
sub_b_imm8_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.b #xx:8,Rd
sub.b #5, r0l ; Immediate 8-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu == h8sx)
sub_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; sub.b #xx:8,@eRd
mov #byte_dest, er0
sub.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst
;;; .word 0x7d00
;;; .word 0xa105
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L1
fail
.L1:
sub_b_imm8_rdpostinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; sub.b #xx:8,@eRd+
mov #byte_dest, er0
sub.b #5:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xa105
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte, er0 ; er0 still contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x9b, r0l
beq .L2
fail
.L2:
sub_b_imm8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; sub.b #xx:8,@eRd-
mov #byte_dest, er0
sub.b #5:8, @er0- ; Immediate 8-bit src, reg post-decr dest
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xa105
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte, er0 ; er0 still contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x96, r0l
beq .L3
fail
.L3:
.endif
sub_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.b Rs,Rd
mov.b #5, r0h
sub.b r0h, r0l ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x05a0 r0 ; sub result: a5 - 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
sub_b_reg8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; sub.b rs8,@eRd ; Subx to register indirect
mov #byte_dest, er0
mov #5, r1l
sub.b r1l, @er0 ; reg8 src, reg indirect dest
;;; .word 0x7d00
;;; .word 0x1890
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x91, r0l
beq .L4
fail
.L4:
sub_b_reg8_rdpostinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; sub.b rs8,@eRd+ ; Subx to register indirect
mov #byte_dest, er0
mov #5, r1l
sub.b r1l, @er0+ ; reg8 src, reg indirect dest
;;; .word 0x0179
;;; .word 0x8039
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte er0 ; er0 still contains address plus one
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x8c, r0l
beq .L5
fail
.L5:
sub_b_reg8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; sub.b rs8,@eRd- ; Subx to register indirect
mov #byte_dest, er0
mov #5, r1l
sub.b r1l, @er0- ; reg8 src, reg indirect dest
;;; .word 0x0179
;;; .word 0xa039
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte er0 ; er0 still contains address minus one
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x87, r0l
beq .L6
fail
.L6:
.endif
pass
exit 0

91
sim/testsuite/sim/h8300/sub.l.s

@ -1,91 +0,0 @@
# Hitachi H8 testcase 'sub.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ;
sub_l_imm3: ; 3-bit immediate mode only for h8sx
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.l #xx:3,eRd ; Immediate 3-bit operand
sub.l #7:3, er0
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
sub_l_imm16: ; sub immediate 16-bit value
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.l #xx:16,eRd ; Immediate 16-bit operand
sub.l #0x1111:16, er0
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x9494 r0 ; sub result: a5a5 - 1111
test_h_gr32 0xa5a59494 er0 ; sub result: a5a5 - 1111
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
sub_l_imm32:
;; sub.l immediate not available in h8300 mode.
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.l #xx:32,Rd
sub.l #0x11111111, er0 ; Immediate 32-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
sub.l.reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; add.l Rs,Rd
mov.l #0x11111111, er1
sub.l er1, er0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111
test_h_gr32 0x11111111 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

78
sim/testsuite/sim/h8300/sub.w.s

@ -1,78 +0,0 @@
# Hitachi H8 testcase 'sub.w'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
sub_w_imm3: ; sub.w immediate not available in h8300 mode.
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.w #xx:3,Rd ; Immediate 3-bit operand
sub.w #7:3, r0
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa59e r0 ; sub result: a5a5 - 7
test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu) ; non-zero means h8300h, s, or sx
sub_w_imm16: ; sub.w immediate not available in h8300 mode.
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.w #xx:16,Rd
sub.w #0x111, r0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111
test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
sub.w.reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.w Rs,Rd
mov.w #0x111, r1
sub.w r1, r0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111
test_h_gr16 0x0111 r1
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111
test_h_gr32 0xa5a50111 er1
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

327
sim/testsuite/sim/h8300/xor.b.s

@ -1,327 +0,0 @@
# Hitachi H8 testcase 'xor.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# xor.b #xx:8, rd ; d rd xxxxxxxx
# xor.b #xx:8, @erd ; 7 d rd ???? d ???? xxxxxxxx
# xor.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? d ???? xxxxxxxx
# xor.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? d ???? xxxxxxxx
# xor.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? d ???? xxxxxxxx
# xor.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? d ???? xxxxxxxx
# xor.b rs, rd ; 1 5 rs rd
# xor.b reg8, @erd ; 7 d rd ???? 1 5 rs ????
# xor.b reg8, @erd+ ; 0 1 7 9 8 rd 5 rs
# xor.b reg8, @erd- ; 0 1 7 9 a rd 5 rs
# xor.b reg8, @+erd ; 0 1 7 9 9 rd 5 rs
# xor.b reg8, @-erd ; 0 1 7 9 b rd 5 rs
#
# Coming soon:
# ...
.data
pre_byte: .byte 0
byte_dest: .byte 0xa5
post_byte: .byte 0
start
xor_b_imm8_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.b #xx:8,Rd
xor.b #0xff, r0l ; Immediate 8-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa55a r0 ; xor result: a5 ^ ff
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a55a er0 ; xor result: a5 ^ ff
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
xor_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; xor.b #xx:8,@eRd
mov #byte_dest, er0
xor.b #0xff:8, @er0 ; Immediate 8-bit src, reg indirect dst
;;; .word 0x7d00
;;; .word 0xd0ff
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest, er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the xor to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x5a, r0l
beq .L1
fail
.L1:
xor_b_imm8_postinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; xor.b #xx:8,@eRd+
mov #byte_dest, er0
xor.b #0xff:8, @er0+ ; Immediate 8-bit src, reg indirect dst
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xd0ff
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte, er0 ; er0 contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the xor to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L2
fail
.L2:
xor_b_imm8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; xor.b #xx:8,@eRd-
mov #byte_dest, er0
xor.b #0xff:8, @er0- ; Immediate 8-bit src, reg indirect dst
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xd0ff
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte, er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the xor to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x5a, r0l
beq .L3
fail
.L3:
.endif
xor_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.b Rs,Rd
mov.b #0xff, r0h
xor.b r0h, r0l ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xff5a r0 ; xor result: a5 ^ ff
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5ff5a er0 ; xor result: a5 ^ ff
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
xor_b_reg8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; xor.b rs8,@eRd ; xor reg8 to register indirect
mov #byte_dest, er0
mov #0xff, r1l
xor.b r1l, @er0 ; reg8 src, reg indirect dest
;;; .word 0x7d00
;;; .word 0x1590
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L4
fail
.L4:
xor_b_reg8_rdpostinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; xor.b rs8,@eRd+ ; xor reg8 to register post-increment
mov #byte_dest, er0
mov #0xff, r1l
xor.b r1l, @er0+ ; reg8 src, reg post-increment dest
;;; .word 0x0179
;;; .word 0x8059
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x5a, r0l
beq .L5
fail
.L5:
xor_b_reg8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; xor.b rs8,@eRd- ; xor reg8 to register post-decrement
mov #byte_dest, er0
mov #0xff, r1l
xor.b r1l, @er0- ; reg8 src, reg indirect dest
;;; .word 0x0179
;;; .word 0xa059
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L6
fail
.L6:
xorc_imm8_ccr:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; xorc #xx:8,ccr
test_neg_clear
xorc #0x8, ccr ; Immediate 8-bit operand (neg flag)
test_neg_set
xorc #0x8, ccr
test_neg_clear
test_zero_clear
xorc #0x4, ccr ; Immediate 8-bit operand (zero flag)
test_zero_set
xorc #0x4, ccr
test_zero_clear
test_ovf_clear
xorc #0x2, ccr ; Immediate 8-bit operand (overflow flag)
test_ovf_set
xorc #0x2, ccr
test_ovf_clear
test_carry_clear
xorc #0x1, ccr ; Immediate 8-bit operand (carry flag)
test_carry_set
xorc #0x1, ccr
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0

77
sim/testsuite/sim/h8300/xor.l.s

@ -1,77 +0,0 @@
# Hitachi H8 testcase 'xor.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx.
xor_l_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.l #xx:16,Rd
xor.l #0xffff:16, er0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5a5a5 | ffff
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
xor_l_imm32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.l #xx:32,Rd
xor.l #0xffffffff, er0 ; Immediate 32-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
xor_l_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.l Rs,Rd
mov.l #0xffffffff, er1
xor.l er1, er0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff
test_h_gr32 0xffffffff er1 ; Make sure er1 is unchanged
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

61
sim/testsuite/sim/h8300/xor.w.s

@ -1,61 +0,0 @@
# Hitachi H8 testcase 'xor.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu) ; non-zero means h8300h, s, or sx
xor_w_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.w #xx:16,Rd
xor.w #0xffff, r0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
xor_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.w Rs,Rd
mov.w #0xffff, r1
xor.w r1, r0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff
test_h_gr16 0xffff r1 ; Make sure r1 is unchanged
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff
test_h_gr32 0xa5a5ffff er1 ; Make sure er1 is unchanged
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0