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* gencode.c (build_mips16_operands): Fix base PC value for PC
relative operands. (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a jal instruction. * interp.c (simJALDELAYSLOT): Define. (JALDELAYSLOT): Define. (INDELAYSLOT, INJALDELAYSLOT): Define. (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
This commit is contained in:
Ian Lance Taylor
@ -1,3 +1,33 @@
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Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
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* gencode.c (build_mips16_operands): Fix base PC value for PC
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relative operands.
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(build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
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jal instruction.
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* interp.c (simJALDELAYSLOT): Define.
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(JALDELAYSLOT): Define.
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(INDELAYSLOT, INJALDELAYSLOT): Define.
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(simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
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Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
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* gencode.c (build_instruction): Use !ByteSwapMem instead of
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BigEndianMem.
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* interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
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(BigEndianMem): Rename to ByteSwapMem and change sense.
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(BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
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BigEndianMem references to !ByteSwapMem.
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(set_endianness): New function, with prototype.
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(sim_open): Call set_endianness.
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(sim_info): Use simBE instead of BigEndianMem.
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(xfer_direct_word, xfer_direct_long, swap_direct_word,
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swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
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xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
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ifdefs, keeping the prototype declaration.
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(swap_word): Rewrite correctly.
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(ColdReset): Delete references to CONFIG. Delete endianness related
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code; moved to set_endianness.
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Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
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* gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
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@ -954,10 +954,10 @@ build_mips16_operands (bitmap)
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{
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int j;
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printf ("PC & ~ (uword64) 1");
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printf ("((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : IPC) & ~ (uword64) 1)");
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for (j = 0; j < opindex; j++)
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if (ops[j]->shift != 0)
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printf (" & 0x%x", ~ ((1 << op->shift) - 1));
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printf (" & ~ (uword64) 0x%x", (1 << ops[j]->shift) - 1);
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}
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else if ((op->flags & MIPS16_ZERO) != 0)
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printf ("0");
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@ -1867,7 +1867,10 @@ build_instruction (doisa, features, mips16, insn)
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printf(" op1 = WORD64LO(op1);\n");
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printf(" /* NOTE: The jump occurs AFTER the next instruction has been executed */\n");
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printf(" DSPC = op1;\n");
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printf(" DELAYSLOT();\n");
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if (insn->flags & LINK)
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printf(" JALDELAYSLOT();\n");
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else
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printf(" DELAYSLOT();\n");
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break ;
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case BRANCH: /* execute delay slot instruction before branch unless (LIKELY && branch_not_taken) */
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@ -231,9 +231,6 @@ static ut_reg EPC = 0; /* Exception PC */
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static FP_formats fpr_state[32];
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#endif /* HASFPU */
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/* VR4300 CP0 configuration register: */
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static unsigned int CONFIG = 0;
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/* The following are internal simulator state variables: */
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static ut_reg IPC = 0; /* internal Instruction PC */
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static ut_reg DSPC = 0; /* delay-slot PC */
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@ -257,13 +254,6 @@ static ut_reg DSPC = 0; /* delay-slot PC */
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#define status_ERL (1 << 2) /* Error level */
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#define status_RP (1 << 27) /* Reduced Power mode */
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#define config_EP_mask (0xF)
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#define config_EP_shift (27)
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#define config_EP_D (0x0)
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#define config_EP_DxxDxx (0x6)
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#define config_BE (1 << 15)
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#define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
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#if defined(HASFPU)
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@ -331,6 +321,7 @@ static ut_reg pending_slot_value[PSLOTS];
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static void dotrace PARAMS((FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...));
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static void sim_warning PARAMS((char *fmt,...));
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extern void sim_error PARAMS((char *fmt,...));
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static void set_endianness PARAMS((void));
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static void ColdReset PARAMS((void));
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static int AddressTranslation PARAMS((uword64 vAddr,int IorD,int LorS,uword64 *pAddr,int *CCA,int host,int raw));
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static void StoreMemory PARAMS((int CCA,int AccessLength,uword64 MemElem,uword64 pAddr,uword64 vAddr,int raw));
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@ -399,14 +390,9 @@ static ut_reg HLPC = 0;
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/* UserMode */
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#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
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/* BigEndianMem */
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/* Hardware configuration. Affects endianness of LoadMemory and
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StoreMemory and the endianness of Kernel and Supervisor mode
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execution. The value is 0 for little-endian; 1 for big-endian. */
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#define BigEndianMem ((CONFIG & config_BE) ? 1 : 0)
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/* NOTE: Problems will occur if the simulator memory model does not
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match the host program expectation. i.e. if the host is writing
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big-endian values to a little-endian memory model. */
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/* ByteSwapMem */
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/* This is true if the host and target have different endianness. */
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#define ByteSwapMem (!(state & simHOSTBE) != !(state & simBE))
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/* ReverseEndian */
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/* This mode is selected if in User mode with the RE bit being set in
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@ -418,8 +404,8 @@ static ut_reg HLPC = 0;
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/* The endianness for load and store instructions (0=little;1=big). In
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User mode this endianness may be switched by setting the state_RE
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bit in the SR register. Thus, BigEndianCPU may be computed as
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(BigEndienMem EOR ReverseEndian). */
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#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
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(!ByteSwapMem EOR ReverseEndian). */
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#define BigEndianCPU (!ByteSwapMem ^ ReverseEndian) /* Already bits */
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#if !defined(FASTSIM) || defined(PROFILE)
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/* At the moment these values will be the same, since we do not have
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@ -449,6 +435,7 @@ static unsigned int pipeline_ticks = 0;
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#define simEXCEPTION (1 << 26) /* 0 = no exception; 1 = exception has occurred */
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#define simEXIT (1 << 27) /* 0 = do nothing; 1 = run-time exit() processing */
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#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
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#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
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static unsigned int state = 0;
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static unsigned int rcexit = 0; /* _exit() reason code holder */
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@ -459,11 +446,19 @@ static unsigned int rcexit = 0; /* _exit() reason code holder */
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state |= simDELAYSLOT;\
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}
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#define JALDELAYSLOT() {\
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DELAYSLOT ();\
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state |= simJALDELAYSLOT;\
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}
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#define NULLIFY() {\
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state &= ~simDELAYSLOT;\
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state |= simSKIPNEXT;\
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}
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#define INDELAYSLOT() ((state & simDELAYSLOT) != 0)
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#define INJALDELAYSLOT() ((state & simJALDELAYSLOT) != 0)
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#define K0BASE (0x80000000)
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#define K0SIZE (0x20000000)
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#define K1BASE (0xA0000000)
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@ -544,6 +539,8 @@ sim_open (args)
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state |= simHOSTBE; /* big-endian host */
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}
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set_endianness ();
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#if defined(HASFPU)
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/* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
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and DOUBLE binary formats. This is a bit nasty, requiring that we
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@ -1057,7 +1054,7 @@ sim_write (addr,buffer,size)
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/* We need to perform the following magic to ensure that that
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bytes are written into same byte positions in the target memory
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world, regardless of the endianness of the host. */
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if (BigEndianMem) {
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if (!ByteSwapMem) {
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value = ((uword64)(*buffer++) << 8);
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value |= ((uword64)(*buffer++) << 0);
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} else {
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@ -1074,7 +1071,7 @@ sim_write (addr,buffer,size)
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int cca;
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if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) {
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uword64 value;
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if (BigEndianMem) {
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if (!ByteSwapMem) {
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value = ((uword64)(*buffer++) << 24);
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value |= ((uword64)(*buffer++) << 16);
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value |= ((uword64)(*buffer++) << 8);
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@ -1095,7 +1092,7 @@ sim_write (addr,buffer,size)
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int cca;
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if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) {
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uword64 value;
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if (BigEndianMem) {
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if (!ByteSwapMem) {
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value = ((uword64)(*buffer++) << 56);
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value |= ((uword64)(*buffer++) << 48);
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value |= ((uword64)(*buffer++) << 40);
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@ -1278,7 +1275,7 @@ sim_info (verbose)
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callback->printf_filtered(callback,"MIPS %d-bit simulator\n",(PROCESSOR_64BIT ? 64 : 32));
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callback->printf_filtered(callback,"%s endian memory model\n",(BigEndianMem ? "Big" : "Little"));
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callback->printf_filtered(callback,"%s endian memory model\n",(state & simBE ? "Big" : "Little"));
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callback->printf_filtered(callback,"0x%08X bytes of memory at 0x%08X%08X\n",(unsigned int)membank_size,WORD64HI(membank_base),WORD64LO(membank_base));
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@ -1962,67 +1959,37 @@ void dotrace(FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...
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simulation, at the cost of increasing the image and source size. */
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static unsigned int
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#ifdef _MSC_VER
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xfer_direct_word(unsigned char *memory)
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#else
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xfer_direct_word(memory)
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unsigned char *memory;
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#endif
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{
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return *((unsigned int *)memory);
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}
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static uword64
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#ifdef _MSC_VER
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xfer_direct_long(unsigned char *memory)
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#else
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xfer_direct_long(memory)
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unsigned char *memory;
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#endif
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{
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return *((uword64 *)memory);
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}
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static unsigned int
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#ifdef _MSC_VER
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swap_direct_word(unsigned int data)
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#else
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swap_direct_word(data)
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unsigned int data;
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#endif
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{
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return data;
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}
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static uword64
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#ifdef _MSC_VER
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swap_direct_long(uword64 data)
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#else
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swap_direct_long(data)
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uword64 data;
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#endif
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{
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return data;
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}
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static unsigned int
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#ifdef _MSC_VER
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xfer_big_word(unsigned char *memory)
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#else
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xfer_big_word(memory)
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unsigned char *memory;
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#endif
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{
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return ((memory[0] << 24) | (memory[1] << 16) | (memory[2] << 8) | memory[3]);
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}
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static uword64
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#ifdef _MSC_VER
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xfer_big_long(unsigned char *memory)
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#else
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xfer_big_long(memory)
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unsigned char *memory;
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#endif
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{
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return (((uword64)memory[0] << 56) | ((uword64)memory[1] << 48)
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| ((uword64)memory[2] << 40) | ((uword64)memory[3] << 32)
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@ -2031,23 +1998,13 @@ xfer_big_long(memory)
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}
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static unsigned int
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#ifdef _MSC_VER
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xfer_little_word(unsigned char *memory)
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#else
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xfer_little_word(memory)
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unsigned char *memory;
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#endif
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{
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return ((memory[3] << 24) | (memory[2] << 16) | (memory[1] << 8) | memory[0]);
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}
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static uword64
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#ifdef _MSC_VER
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xfer_little_long(unsigned char *memory)
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#else
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xfer_little_long(memory)
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unsigned char *memory;
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#endif
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{
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return (((uword64)memory[7] << 56) | ((uword64)memory[6] << 48)
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| ((uword64)memory[5] << 40) | ((uword64)memory[4] << 32)
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@ -2056,27 +2013,16 @@ xfer_little_long(memory)
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}
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static unsigned int
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#ifdef _MSC_VER
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swap_word(unsigned int data)
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#else
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swap_word(data)
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unsigned int data;
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#endif
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{
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unsigned int result;
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result = data ^ ((data << 16) | (data >> 16));
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result &= ~0x00FF0000;
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data = (data << 24) | (data >> 8);
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return data ^ (result >> 8);
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result = (((data & 0xff) << 24) | ((data & 0xff00) << 8)
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| ((data >> 8) & 0xff00) | ((data >> 24) & 0xff));
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return result;
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}
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static uword64
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#ifdef _MSC_VER
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swap_long(uword64 data)
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#else
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swap_long(data)
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uword64 data;
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#endif
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{
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unsigned int tmphi = WORD64HI(data);
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unsigned int tmplo = WORD64LO(data);
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@ -2090,6 +2036,36 @@ swap_long(data)
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/*-- simulator engine -------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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static void
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set_endianness ()
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{
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/* In reality this check should be performed at various points
|
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within the simulation, since it is possible to change the
|
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endianness of user programs. However, we perform the check here
|
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to ensure that the start-of-day values agree. */
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if (target_byte_order == 4321)
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state |= simBE;
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/* ??? This is a lot more code than is necessary to solve the problem.
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It would be simpler to handle this like the SH simulator. */
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if (!ByteSwapMem) {
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host_read_word = xfer_direct_word;
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host_read_long = xfer_direct_long;
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host_swap_word = swap_direct_word;
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host_swap_long = swap_direct_long;
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} else if (state & simHOSTBE) {
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host_read_word = xfer_little_word;
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host_read_long = xfer_little_long;
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host_swap_word = swap_word;
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host_swap_long = swap_long;
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} else { /* HOST little-endian */
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host_read_word = xfer_big_word;
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host_read_long = xfer_big_long;
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host_swap_word = swap_word;
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host_swap_long = swap_long;
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}
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}
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|
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static void
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ColdReset()
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{
|
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@ -2099,10 +2075,6 @@ ColdReset()
|
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|
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SR &= ~(status_SR | status_TS | status_RP);
|
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SR |= (status_ERL | status_BEV);
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/* VR4300 starts in Big-Endian mode */
|
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CONFIG &= ~(config_EP_mask << config_EP_shift);
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CONFIG |= ((config_EP_D << config_EP_shift) | config_BE);
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/* TODO: The VR4300 CONFIG register is not modelled fully at the moment */
|
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|
||||
#if defined(HASFPU) && (GPRLEN == (64))
|
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/* Cheat and allow access to the complete register set immediately: */
|
||||
@ -2127,35 +2099,6 @@ ColdReset()
|
||||
}
|
||||
#endif /* HASFPU */
|
||||
|
||||
/* In reality this check should be performed at various points
|
||||
within the simulation, since it is possible to change the
|
||||
endianness of user programs. However, we perform the check here
|
||||
to ensure that the start-of-day values agree: */
|
||||
state |= (BigEndianCPU ? simBE : 0);
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if ((target_byte_order == 1234) != !(state & simBE)) {
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||||
fprintf(stderr,"ColdReset: GDB (%s) and simulator (%s) do not agree on target endianness\n",
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target_byte_order == 1234 ? "little" : "big",
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state & simBE ? "big" : "little");
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exit(1);
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}
|
||||
|
||||
if (!(state & simHOSTBE) == !(state & simBE)) {
|
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host_read_word = xfer_direct_word;
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host_read_long = xfer_direct_long;
|
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host_swap_word = swap_direct_word;
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host_swap_long = swap_direct_long;
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} else if (state & simHOSTBE) {
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host_read_word = xfer_little_word;
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||||
host_read_long = xfer_little_long;
|
||||
host_swap_word = swap_word;
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host_swap_long = swap_long;
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} else { /* HOST little-endian */
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||||
host_read_word = xfer_big_word;
|
||||
host_read_long = xfer_big_long;
|
||||
host_swap_word = swap_word;
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host_swap_long = swap_long;
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||||
}
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||||
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||||
return;
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||||
}
|
||||
|
||||
@ -2353,7 +2296,7 @@ LoadMemory(CCA,AccessLength,pAddr,vAddr,IorD,raw)
|
||||
extracts the required bytes. However, to keep performance
|
||||
high we only load the required bytes into the relevant
|
||||
slots. */
|
||||
if (BigEndianMem)
|
||||
if (!ByteSwapMem)
|
||||
switch (AccessLength) { /* big-endian memory */
|
||||
case AccessLength_DOUBLEWORD :
|
||||
value |= ((uword64)mem[index++] << 56);
|
||||
@ -2405,7 +2348,7 @@ LoadMemory(CCA,AccessLength,pAddr,vAddr,IorD,raw)
|
||||
StoreMemory routines to avoid shifting the data before
|
||||
returning or using it. */
|
||||
if (!raw) { /* do nothing for raw accessess */
|
||||
if (BigEndianMem)
|
||||
if (!ByteSwapMem)
|
||||
value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
|
||||
else /* little-endian only needs to be shifted up to the correct byte offset */
|
||||
value <<= ((pAddr & LOADDRMASK) * 8);
|
||||
@ -2483,7 +2426,7 @@ StoreMemory(CCA,AccessLength,MemElem,pAddr,vAddr,raw)
|
||||
printf("DBG: StoreMemory: offset = %d MemElem = 0x%08X%08X\n",(unsigned int)(pAddr & LOADDRMASK),WORD64HI(MemElem),WORD64LO(MemElem));
|
||||
#endif /* DEBUG */
|
||||
|
||||
if (BigEndianMem) {
|
||||
if (!ByteSwapMem) {
|
||||
if (raw)
|
||||
shift = ((7 - AccessLength) * 8);
|
||||
else /* real memory access */
|
||||
@ -2499,7 +2442,7 @@ StoreMemory(CCA,AccessLength,MemElem,pAddr,vAddr,raw)
|
||||
printf("DBG: StoreMemory: shift = %d MemElem = 0x%08X%08X\n",shift,WORD64HI(MemElem),WORD64LO(MemElem));
|
||||
#endif /* DEBUG */
|
||||
|
||||
if (BigEndianMem) {
|
||||
if (!ByteSwapMem) {
|
||||
switch (AccessLength) { /* big-endian memory */
|
||||
case AccessLength_DOUBLEWORD :
|
||||
mem[index++] = (unsigned char)(MemElem >> 56);
|
||||
@ -4040,7 +3983,7 @@ simulate ()
|
||||
printf("DBG: dsstate set before instruction execution - updating PC to 0x%08X%08X\n",WORD64HI(DSPC),WORD64LO(DSPC));
|
||||
#endif /* DEBUG */
|
||||
PC = DSPC;
|
||||
state &= ~simDELAYSLOT;
|
||||
state &= ~(simDELAYSLOT | simJALDELAYSLOT);
|
||||
}
|
||||
|
||||
if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */
|
||||
|
||||
Reference in New Issue
Block a user