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RISC-V: Add T-Head CMO vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadCmo extension, a collection of T-Head specific
cache management operations.
The 'th' prefix and the "XTheadCmo" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
In total XTheadCmo introduces the following 21 instructions:
* DCACHE.{C,CI,I}ALL
* DCACHE.{C,CI,I}{PA,VA,SW} rs1
* DCACHE.C{PAL1,VAL1} rs1
* ICACHE.I{ALL,ALLS}
* ICACHE.I{PA,VA} rs1
* L2CACHE.{C,CI,I}ALL
Contrary to Zicbom, the XTheadCmo instructions don't have a constant
displacement, therefore we have a different syntax for the arguments.
To clarify this is intended behaviour, there is a set of negative test
for Zicbom-style arguments in x-thead-cmo-fail.s.
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
v2:
- Add missing DECLARE_INSN() list
- Fix ordering
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:
Christoph Müllner
committed by
Philipp Tomsich
Philipp Tomsich
parent
fb1737381d
commit
a9ba8bc2d3
@ -1224,6 +1224,7 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
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static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
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{
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{"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{NULL, 0, 0, 0, 0}
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};
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@ -2386,6 +2387,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
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return riscv_subset_supports (rps, "svinval");
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case INSN_CLASS_H:
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return riscv_subset_supports (rps, "h");
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case INSN_CLASS_XTHEADCMO:
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return riscv_subset_supports (rps, "xtheadcmo");
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default:
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rps->error_handler
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(_("internal: unreachable INSN_CLASS_*"));
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@ -2513,6 +2516,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
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return "svinval";
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case INSN_CLASS_H:
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return _("h");
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case INSN_CLASS_XTHEADCMO:
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return "xtheadcmo";
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default:
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rps->error_handler
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(_("internal: unreachable INSN_CLASS_*"));
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@ -704,5 +704,9 @@ extensions supported and provides the location of their
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publicly-released documentation:
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@table @r
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@item XTheadCmo
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The XTheadCmo extension provides instructions for cache management.
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It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
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@end table
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3
gas/testsuite/gas/riscv/x-thead-cmo-fail.d
Normal file
3
gas/testsuite/gas/riscv/x-thead-cmo-fail.d
Normal file
@ -0,0 +1,3 @@
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#as: -march=rv64i_xtheadcmo
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#source: x-thead-cmo-fail.s
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#error_output: x-thead-cmo-fail.l
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22
gas/testsuite/gas/riscv/x-thead-cmo-fail.l
Normal file
22
gas/testsuite/gas/riscv/x-thead-cmo-fail.l
Normal file
@ -0,0 +1,22 @@
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.*: Assembler messages:
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.*: Error: illegal operands `th.dcache.call x1'
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.*: Error: illegal operands `th.dcache.ciall x1'
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.*: Error: illegal operands `th.dcache.iall x1'
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.*: Error: illegal operands `th.dcache.cpa 0\(x1\)'
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.*: Error: illegal operands `th.dcache.cipa 0\(x1\)'
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.*: Error: illegal operands `th.dcache.ipa 0\(x1\)'
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.*: Error: illegal operands `th.dcache.cva 0\(x1\)'
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.*: Error: illegal operands `th.dcache.civa 0\(x1\)'
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.*: Error: illegal operands `th.dcache.iva 0\(x1\)'
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.*: Error: illegal operands `th.dcache.csw 0\(x1\)'
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.*: Error: illegal operands `th.dcache.cisw 0\(x1\)'
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.*: Error: illegal operands `th.dcache.isw 0\(x1\)'
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.*: Error: illegal operands `th.dcache.cpal1 0\(x1\)'
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.*: Error: illegal operands `th.dcache.cval1 0\(x1\)'
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.*: Error: illegal operands `th.icache.iall x1'
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.*: Error: illegal operands `th.icache.ialls x1'
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.*: Error: illegal operands `th.icache.ipa 0\(x1\)'
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.*: Error: illegal operands `th.icache.iva 0\(x1\)'
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.*: Error: illegal operands `th.l2cache.call x1'
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.*: Error: illegal operands `th.l2cache.ciall x1'
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.*: Error: illegal operands `th.l2cache.iall x1'
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22
gas/testsuite/gas/riscv/x-thead-cmo-fail.s
Normal file
22
gas/testsuite/gas/riscv/x-thead-cmo-fail.s
Normal file
@ -0,0 +1,22 @@
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target:
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th.dcache.call x1
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th.dcache.ciall x1
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th.dcache.iall x1
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th.dcache.cpa 0(x1)
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th.dcache.cipa 0(x1)
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th.dcache.ipa 0(x1)
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th.dcache.cva 0(x1)
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th.dcache.civa 0(x1)
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th.dcache.iva 0(x1)
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th.dcache.csw 0(x1)
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th.dcache.cisw 0(x1)
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th.dcache.isw 0(x1)
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th.dcache.cpal1 0(x1)
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th.dcache.cval1 0(x1)
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th.icache.iall x1
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th.icache.ialls x1
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th.icache.ipa 0(x1)
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th.icache.iva 0(x1)
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th.l2cache.call x1
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th.l2cache.ciall x1
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th.l2cache.iall x1
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30
gas/testsuite/gas/riscv/x-thead-cmo.d
Normal file
30
gas/testsuite/gas/riscv/x-thead-cmo.d
Normal file
@ -0,0 +1,30 @@
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#as: -march=rv64i_xtheadcmo
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#source: x-thead-cmo.s
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#objdump: -dr
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+0010000b[ ]+th.dcache.call
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[ ]+[0-9a-f]+:[ ]+0030000b[ ]+th.dcache.ciall
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[ ]+[0-9a-f]+:[ ]+0020000b[ ]+th.dcache.iall
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[ ]+[0-9a-f]+:[ ]+0295000b[ ]+th.dcache.cpa[ ]+a0
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[ ]+[0-9a-f]+:[ ]+02b5800b[ ]+th.dcache.cipa[ ]+a1
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[ ]+[0-9a-f]+:[ ]+02a6000b[ ]+th.dcache.ipa[ ]+a2
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[ ]+[0-9a-f]+:[ ]+0256800b[ ]+th.dcache.cva[ ]+a3
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[ ]+[0-9a-f]+:[ ]+0277000b[ ]+th.dcache.civa[ ]+a4
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[ ]+[0-9a-f]+:[ ]+0267800b[ ]+th.dcache.iva[ ]+a5
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[ ]+[0-9a-f]+:[ ]+0218000b[ ]+th.dcache.csw[ ]+a6
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[ ]+[0-9a-f]+:[ ]+0238800b[ ]+th.dcache.cisw[ ]+a7
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[ ]+[0-9a-f]+:[ ]+0222800b[ ]+th.dcache.isw[ ]+t0
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[ ]+[0-9a-f]+:[ ]+0283000b[ ]+th.dcache.cpal1[ ]+t1
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[ ]+[0-9a-f]+:[ ]+0243800b[ ]+th.dcache.cval1[ ]+t2
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[ ]+[0-9a-f]+:[ ]+0100000b[ ]+th.icache.iall
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[ ]+[0-9a-f]+:[ ]+0110000b[ ]+th.icache.ialls
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[ ]+[0-9a-f]+:[ ]+038e000b[ ]+th.icache.ipa[ ]+t3
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[ ]+[0-9a-f]+:[ ]+030e800b[ ]+th.icache.iva[ ]+t4
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[ ]+[0-9a-f]+:[ ]+0150000b[ ]+th.l2cache.call
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[ ]+[0-9a-f]+:[ ]+0170000b[ ]+th.l2cache.ciall
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[ ]+[0-9a-f]+:[ ]+0160000b[ ]+th.l2cache.iall
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22
gas/testsuite/gas/riscv/x-thead-cmo.s
Normal file
22
gas/testsuite/gas/riscv/x-thead-cmo.s
Normal file
@ -0,0 +1,22 @@
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target:
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th.dcache.call
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th.dcache.ciall
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th.dcache.iall
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th.dcache.cpa a0
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th.dcache.cipa a1
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th.dcache.ipa a2
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th.dcache.cva a3
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th.dcache.civa a4
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th.dcache.iva a5
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th.dcache.csw a6
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th.dcache.cisw a7
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th.dcache.isw t0
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th.dcache.cpal1 t1
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th.dcache.cval1 t2
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th.icache.iall
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th.icache.ialls
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th.icache.ipa t3
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th.icache.iva t4
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th.l2cache.call
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th.l2cache.ciall
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th.l2cache.iall
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@ -2113,6 +2113,49 @@
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#define MASK_CBO_INVAL 0xfff07fff
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#define MATCH_CBO_ZERO 0x40200f
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#define MASK_CBO_ZERO 0xfff07fff
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/* Vendor-specific (T-Head) XTheadCmo instructions. */
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#define MATCH_TH_DCACHE_CALL 0x0010000b
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#define MASK_TH_DCACHE_CALL 0xffffffff
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#define MATCH_TH_DCACHE_CIALL 0x0030000b
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#define MASK_TH_DCACHE_CIALL 0xffffffff
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#define MATCH_TH_DCACHE_IALL 0x0020000b
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#define MASK_TH_DCACHE_IALL 0xffffffff
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#define MATCH_TH_DCACHE_CPA 0x0290000b
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#define MASK_TH_DCACHE_CPA 0xfff07fff
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#define MATCH_TH_DCACHE_CIPA 0x02b0000b
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#define MASK_TH_DCACHE_CIPA 0xfff07fff
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#define MATCH_TH_DCACHE_IPA 0x02a0000b
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#define MASK_TH_DCACHE_IPA 0xfff07fff
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#define MATCH_TH_DCACHE_CVA 0x0250000b
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#define MASK_TH_DCACHE_CVA 0xfff07fff
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#define MATCH_TH_DCACHE_CIVA 0x0270000b
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#define MASK_TH_DCACHE_CIVA 0xfff07fff
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#define MATCH_TH_DCACHE_IVA 0x0260000b
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#define MASK_TH_DCACHE_IVA 0xfff07fff
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#define MATCH_TH_DCACHE_CSW 0x0210000b
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#define MASK_TH_DCACHE_CSW 0xfff07fff
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#define MATCH_TH_DCACHE_CISW 0x0230000b
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#define MASK_TH_DCACHE_CISW 0xfff07fff
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#define MATCH_TH_DCACHE_ISW 0x0220000b
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#define MASK_TH_DCACHE_ISW 0xfff07fff
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#define MATCH_TH_DCACHE_CPAL1 0x0280000b
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#define MASK_TH_DCACHE_CPAL1 0xfff07fff
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#define MATCH_TH_DCACHE_CVAL1 0x0240000b
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#define MASK_TH_DCACHE_CVAL1 0xfff07fff
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#define MATCH_TH_ICACHE_IALL 0x0100000b
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#define MASK_TH_ICACHE_IALL 0xffffffff
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#define MATCH_TH_ICACHE_IALLS 0x0110000b
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#define MASK_TH_ICACHE_IALLS 0xffffffff
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#define MATCH_TH_ICACHE_IPA 0x0380000b
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#define MASK_TH_ICACHE_IPA 0xfff07fff
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#define MATCH_TH_ICACHE_IVA 0x0300000b
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#define MASK_TH_ICACHE_IVA 0xfff07fff
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#define MATCH_TH_L2CACHE_CALL 0x0150000b
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#define MASK_TH_L2CACHE_CALL 0xffffffff
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#define MATCH_TH_L2CACHE_CIALL 0x0170000b
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#define MASK_TH_L2CACHE_CIALL 0xffffffff
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#define MATCH_TH_L2CACHE_IALL 0x0160000b
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#define MASK_TH_L2CACHE_IALL 0xffffffff
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/* Unprivileged Counter/Timers CSR addresses. */
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#define CSR_CYCLE 0xc00
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#define CSR_TIME 0xc01
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@ -2852,6 +2895,28 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
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DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
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DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
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DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
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/* Vendor-specific (T-Head) XTheadCmo instructions. */
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DECLARE_INSN(th_dcache_call, MATCH_TH_DCACHE_CALL, MASK_TH_DCACHE_CALL)
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DECLARE_INSN(th_dcache_ciall, MATCH_TH_DCACHE_CIALL, MASK_TH_DCACHE_CIALL)
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DECLARE_INSN(th_dcache_iall, MATCH_TH_DCACHE_IALL, MASK_TH_DCACHE_IALL)
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DECLARE_INSN(th_dcache_cpa, MATCH_TH_DCACHE_CPA, MASK_TH_DCACHE_CPA)
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DECLARE_INSN(th_dcache_cipa, MATCH_TH_DCACHE_CIPA, MASK_TH_DCACHE_CIPA)
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DECLARE_INSN(th_dcache_ipa, MATCH_TH_DCACHE_IPA, MASK_TH_DCACHE_IPA)
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DECLARE_INSN(th_dcache_cva, MATCH_TH_DCACHE_CVA, MASK_TH_DCACHE_CVA)
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DECLARE_INSN(th_dcache_civa, MATCH_TH_DCACHE_CIVA, MASK_TH_DCACHE_CIVA)
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DECLARE_INSN(th_dcache_iva, MATCH_TH_DCACHE_IVA, MASK_TH_DCACHE_IVA)
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DECLARE_INSN(th_dcache_csw, MATCH_TH_DCACHE_CSW, MASK_TH_DCACHE_CSW)
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DECLARE_INSN(th_dcache_cisw, MATCH_TH_DCACHE_CISW, MASK_TH_DCACHE_CISW)
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DECLARE_INSN(th_dcache_isw, MATCH_TH_DCACHE_ISW, MASK_TH_DCACHE_ISW)
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DECLARE_INSN(th_dcache_cpal1, MATCH_TH_DCACHE_CPAL1, MASK_TH_DCACHE_CPAL1)
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DECLARE_INSN(th_dcache_cval1, MATCH_TH_DCACHE_CVAL1, MASK_TH_DCACHE_CVAL1)
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DECLARE_INSN(th_icache_iall, MATCH_TH_ICACHE_IALL, MASK_TH_ICACHE_IALL)
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DECLARE_INSN(th_icache_ialls, MATCH_TH_ICACHE_IALLS, MASK_TH_ICACHE_IALLS)
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DECLARE_INSN(th_icache_ipa, MATCH_TH_ICACHE_IPA, MASK_TH_ICACHE_IPA)
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DECLARE_INSN(th_icache_iva, MATCH_TH_ICACHE_IVA, MASK_TH_ICACHE_IVA)
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DECLARE_INSN(th_l2cache_call, MATCH_TH_L2CACHE_CALL, MASK_TH_L2CACHE_CALL)
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DECLARE_INSN(th_l2cache_ciall, MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL)
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DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL)
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#endif /* DECLARE_INSN */
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#ifdef DECLARE_CSR
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/* Unprivileged Counter/Timers CSRs. */
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@ -398,6 +398,7 @@ enum riscv_insn_class
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INSN_CLASS_ZICBOP,
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INSN_CLASS_ZICBOZ,
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INSN_CLASS_H,
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INSN_CLASS_XTHEADCMO,
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};
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/* This structure holds information for a particular instruction. */
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@ -1825,6 +1825,31 @@ const struct riscv_opcode riscv_opcodes[] =
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{"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
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{"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
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/* Vendor-specific (T-Head) XTheadCmo instructions. */
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{"th.dcache.call", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_DCACHE_CALL, MASK_TH_DCACHE_CALL, match_opcode, 0},
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{"th.dcache.ciall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_DCACHE_CIALL, MASK_TH_DCACHE_CIALL, match_opcode, 0},
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{"th.dcache.iall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_DCACHE_IALL, MASK_TH_DCACHE_IALL, match_opcode, 0},
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{"th.dcache.cpa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CPA, MASK_TH_DCACHE_CPA, match_opcode, 0},
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{"th.dcache.cipa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CIPA, MASK_TH_DCACHE_CIPA, match_opcode, 0},
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{"th.dcache.ipa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_IPA, MASK_TH_DCACHE_IPA, match_opcode, 0},
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{"th.dcache.cva", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CVA, MASK_TH_DCACHE_CVA, match_opcode, 0},
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{"th.dcache.civa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CIVA, MASK_TH_DCACHE_CIVA, match_opcode, 0},
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{"th.dcache.iva", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_IVA, MASK_TH_DCACHE_IVA, match_opcode, 0},
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{"th.dcache.csw", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CSW, MASK_TH_DCACHE_CSW, match_opcode, 0},
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{"th.dcache.cisw", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CISW, MASK_TH_DCACHE_CISW, match_opcode, 0},
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{"th.dcache.isw", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_ISW, MASK_TH_DCACHE_ISW, match_opcode, 0},
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{"th.dcache.cpal1", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CPAL1, MASK_TH_DCACHE_CPAL1, match_opcode, 0},
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{"th.dcache.cval1", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CVAL1, MASK_TH_DCACHE_CVAL1, match_opcode, 0},
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{"th.icache.iall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_ICACHE_IALL, MASK_TH_ICACHE_IALL, match_opcode, 0},
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{"th.icache.ialls", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_ICACHE_IALLS, MASK_TH_ICACHE_IALLS, match_opcode, 0},
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{"th.icache.ipa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_ICACHE_IPA, MASK_TH_ICACHE_IPA, match_opcode, 0},
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{"th.icache.iva", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_ICACHE_IVA, MASK_TH_ICACHE_IVA, match_opcode, 0},
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|
||||
{"th.l2cache.call", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_CALL, MASK_TH_L2CACHE_CALL, match_opcode, 0},
|
||||
{"th.l2cache.ciall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL, match_opcode, 0},
|
||||
{"th.l2cache.iall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL, match_opcode, 0},
|
||||
|
||||
/* Terminate the list. */
|
||||
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user