RISC-V: Add T-Head CMO vendor extension

T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadCmo extension, a collection of T-Head specific
cache management operations.
The 'th' prefix and the "XTheadCmo" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).

In total XTheadCmo introduces the following 21 instructions:

* DCACHE.{C,CI,I}ALL
* DCACHE.{C,CI,I}{PA,VA,SW} rs1
* DCACHE.C{PAL1,VAL1} rs1
* ICACHE.I{ALL,ALLS}
* ICACHE.I{PA,VA} rs1
* L2CACHE.{C,CI,I}ALL

Contrary to Zicbom, the XTheadCmo instructions don't have a constant
displacement, therefore we have a different syntax for the arguments.
To clarify this is intended behaviour, there is a set of negative test
for Zicbom-style arguments in x-thead-cmo-fail.s.

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

v2:
- Add missing DECLARE_INSN() list
- Fix ordering

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

include/opcode/riscv-opc.h

@@ -2113,6 +2113,49 @@
 #define MASK_CBO_INVAL 0xfff07fff
 #define MATCH_CBO_ZERO 0x40200f
 #define MASK_CBO_ZERO 0xfff07fff
+/* Vendor-specific (T-Head) XTheadCmo instructions.  */
+#define MATCH_TH_DCACHE_CALL 0x0010000b
+#define MASK_TH_DCACHE_CALL 0xffffffff
+#define MATCH_TH_DCACHE_CIALL 0x0030000b
+#define MASK_TH_DCACHE_CIALL 0xffffffff
+#define MATCH_TH_DCACHE_IALL 0x0020000b
+#define MASK_TH_DCACHE_IALL 0xffffffff
+#define MATCH_TH_DCACHE_CPA 0x0290000b
+#define MASK_TH_DCACHE_CPA 0xfff07fff
+#define MATCH_TH_DCACHE_CIPA 0x02b0000b
+#define MASK_TH_DCACHE_CIPA 0xfff07fff
+#define MATCH_TH_DCACHE_IPA 0x02a0000b
+#define MASK_TH_DCACHE_IPA 0xfff07fff
+#define MATCH_TH_DCACHE_CVA 0x0250000b
+#define MASK_TH_DCACHE_CVA 0xfff07fff
+#define MATCH_TH_DCACHE_CIVA 0x0270000b
+#define MASK_TH_DCACHE_CIVA 0xfff07fff
+#define MATCH_TH_DCACHE_IVA 0x0260000b
+#define MASK_TH_DCACHE_IVA 0xfff07fff
+#define MATCH_TH_DCACHE_CSW 0x0210000b
+#define MASK_TH_DCACHE_CSW 0xfff07fff
+#define MATCH_TH_DCACHE_CISW 0x0230000b
+#define MASK_TH_DCACHE_CISW 0xfff07fff
+#define MATCH_TH_DCACHE_ISW 0x0220000b
+#define MASK_TH_DCACHE_ISW 0xfff07fff
+#define MATCH_TH_DCACHE_CPAL1 0x0280000b
+#define MASK_TH_DCACHE_CPAL1 0xfff07fff
+#define MATCH_TH_DCACHE_CVAL1 0x0240000b
+#define MASK_TH_DCACHE_CVAL1 0xfff07fff
+#define MATCH_TH_ICACHE_IALL 0x0100000b
+#define MASK_TH_ICACHE_IALL 0xffffffff
+#define MATCH_TH_ICACHE_IALLS 0x0110000b
+#define MASK_TH_ICACHE_IALLS 0xffffffff
+#define MATCH_TH_ICACHE_IPA 0x0380000b
+#define MASK_TH_ICACHE_IPA 0xfff07fff
+#define MATCH_TH_ICACHE_IVA 0x0300000b
+#define MASK_TH_ICACHE_IVA 0xfff07fff
+#define MATCH_TH_L2CACHE_CALL 0x0150000b
+#define MASK_TH_L2CACHE_CALL 0xffffffff
+#define MATCH_TH_L2CACHE_CIALL 0x0170000b
+#define MASK_TH_L2CACHE_CIALL 0xffffffff
+#define MATCH_TH_L2CACHE_IALL 0x0160000b
+#define MASK_TH_L2CACHE_IALL 0xffffffff
 /* Unprivileged Counter/Timers CSR addresses.  */
 #define CSR_CYCLE 0xc00
 #define CSR_TIME 0xc01
@@ -2852,6 +2895,28 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
 DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
 DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
 DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
+/* Vendor-specific (T-Head) XTheadCmo instructions.  */
+DECLARE_INSN(th_dcache_call, MATCH_TH_DCACHE_CALL, MASK_TH_DCACHE_CALL)
+DECLARE_INSN(th_dcache_ciall, MATCH_TH_DCACHE_CIALL, MASK_TH_DCACHE_CIALL)
+DECLARE_INSN(th_dcache_iall, MATCH_TH_DCACHE_IALL, MASK_TH_DCACHE_IALL)
+DECLARE_INSN(th_dcache_cpa, MATCH_TH_DCACHE_CPA, MASK_TH_DCACHE_CPA)
+DECLARE_INSN(th_dcache_cipa, MATCH_TH_DCACHE_CIPA, MASK_TH_DCACHE_CIPA)
+DECLARE_INSN(th_dcache_ipa, MATCH_TH_DCACHE_IPA, MASK_TH_DCACHE_IPA)
+DECLARE_INSN(th_dcache_cva, MATCH_TH_DCACHE_CVA, MASK_TH_DCACHE_CVA)
+DECLARE_INSN(th_dcache_civa, MATCH_TH_DCACHE_CIVA, MASK_TH_DCACHE_CIVA)
+DECLARE_INSN(th_dcache_iva, MATCH_TH_DCACHE_IVA, MASK_TH_DCACHE_IVA)
+DECLARE_INSN(th_dcache_csw, MATCH_TH_DCACHE_CSW, MASK_TH_DCACHE_CSW)
+DECLARE_INSN(th_dcache_cisw, MATCH_TH_DCACHE_CISW, MASK_TH_DCACHE_CISW)
+DECLARE_INSN(th_dcache_isw, MATCH_TH_DCACHE_ISW, MASK_TH_DCACHE_ISW)
+DECLARE_INSN(th_dcache_cpal1, MATCH_TH_DCACHE_CPAL1, MASK_TH_DCACHE_CPAL1)
+DECLARE_INSN(th_dcache_cval1, MATCH_TH_DCACHE_CVAL1, MASK_TH_DCACHE_CVAL1)
+DECLARE_INSN(th_icache_iall, MATCH_TH_ICACHE_IALL, MASK_TH_ICACHE_IALL)
+DECLARE_INSN(th_icache_ialls, MATCH_TH_ICACHE_IALLS, MASK_TH_ICACHE_IALLS)
+DECLARE_INSN(th_icache_ipa, MATCH_TH_ICACHE_IPA, MASK_TH_ICACHE_IPA)
+DECLARE_INSN(th_icache_iva, MATCH_TH_ICACHE_IVA, MASK_TH_ICACHE_IVA)
+DECLARE_INSN(th_l2cache_call, MATCH_TH_L2CACHE_CALL, MASK_TH_L2CACHE_CALL)
+DECLARE_INSN(th_l2cache_ciall, MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL)
+DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL)
 #endif /* DECLARE_INSN */
 #ifdef DECLARE_CSR
 /* Unprivileged Counter/Timers CSRs.  */

include/opcode/riscv.h

@@ -398,6 +398,7 @@ enum riscv_insn_class
   INSN_CLASS_ZICBOP,
   INSN_CLASS_ZICBOZ,
   INSN_CLASS_H,
+  INSN_CLASS_XTHEADCMO,
 };
 
 /* This structure holds information for a particular instruction.  */