espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-26 22:07:58 +08:00
Code Issues Packages Projects Releases Wiki Activity

Make the signess of compares between GPR's explicit using a cast to

Browse Source 
signed_word.
This commit is contained in:
Andrew Cagney
1997-11-11 12:31:24 +00:00
parent 030843d7f8
commit a94c5493a7
2 changed files with 39 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
sim/mips/ChangeLog
View File

@ -6,11 +6,12 @@ Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
(LWXC1, SWXC1): Delete from r5900 instruction set. (LWXC1, SWXC1): Delete from r5900 instruction set.
(end-sanitize-r5900): (end-sanitize-r5900):
(MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
PENDING_FILL versions of instructions. PENDING_FILL versions of instructions. Simplify.
(X): New function. (X): New function.
(MULT, MULTU): Implement separate RD==0 and RD!=0 versions of (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
instructions. instructions.
(BEQZ, ...): Explicitly cast GPR to a signed value. (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
a signed value.
(MTHI, MFHI): Disable code checking HI-LO. (MTHI, MFHI): Disable code checking HI-LO.
* sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh

69
sim/mips/mips.igen
View File

@ -2706,7 +2706,7 @@
*tx19: *tx19:
// end-sanitize-tx19 // end-sanitize-tx19
{ {
GPR[RD] = (GPR[RS] < GPR[RT]); GPR[RD] = ((signed_word) GPR[RS] < (signed_word) GPR[RT]);
} }
@ -2727,7 +2727,7 @@
*tx19: *tx19:
// end-sanitize-tx19 // end-sanitize-tx19
{ {
GPR[RT] = (GPR[RS] < EXTEND16 (IMMEDIATE)); GPR[RT] = ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE));
} }
@ -3158,7 +3158,7 @@
*tx19: *tx19:
// end-sanitize-tx19 // end-sanitize-tx19
{ {
if (GPR[RS] == GPR[RT]) if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
SignalException(Trap, instruction_0); SignalException(Trap, instruction_0);
} }
@ -3179,7 +3179,7 @@
*tx19: *tx19:
// end-sanitize-tx19 // end-sanitize-tx19
{ {
if (GPR[RS] == EXTEND16 (IMMEDIATE)) if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0); SignalException(Trap, instruction_0);
} }
@ -3200,7 +3200,7 @@
*tx19: *tx19:
// end-sanitize-tx19 // end-sanitize-tx19
{ {
if (GPR[RS] >= GPR[RT]) if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
SignalException(Trap, instruction_0); SignalException(Trap, instruction_0);
} }
@ -3221,7 +3221,7 @@
*tx19: *tx19:
// end-sanitize-tx19 // end-sanitize-tx19
{ {
if (GPR[RS] >= EXTEND16 (IMMEDIATE)) if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0); SignalException(Trap, instruction_0);
} }
@ -3284,7 +3284,7 @@
*tx19: *tx19:
// end-sanitize-tx19 // end-sanitize-tx19
{ {
if (GPR[RS] < GPR[RT]) if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
SignalException(Trap, instruction_0); SignalException(Trap, instruction_0);
} }
@ -3305,7 +3305,7 @@
*tx19: *tx19:
// end-sanitize-tx19 // end-sanitize-tx19
{ {
if (GPR[RS] < EXTEND16 (IMMEDIATE)) if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0); SignalException(Trap, instruction_0);
} }
@ -3368,7 +3368,7 @@
*tx19: *tx19:
// end-sanitize-tx19 // end-sanitize-tx19
{ {
if (GPR[RS] != GPR[RT]) if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
SignalException(Trap, instruction_0); SignalException(Trap, instruction_0);
} }
@ -3389,7 +3389,7 @@
*tx19: *tx19:
// end-sanitize-tx19 // end-sanitize-tx19
{ {
if (GPR[RS] != EXTEND16 (IMMEDIATE)) if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0); SignalException(Trap, instruction_0);
} }
@ -4074,7 +4074,7 @@
110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
"ldc1 f<FD>, <OFFSET>(r<BASE>)" "ldc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsII: *mipsII:
*mipsIII: *mipsIII:
*mipsIV: *mipsIV:
@ -4086,30 +4086,17 @@
*tx19: *tx19:
// end-sanitize-tx19 // end-sanitize-tx19
{ {
signed_word offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
{
address_word vaddr = ((uword64)op1 + offset);
address_word paddr; address_word paddr;
int uncached; int uncached;
if ((vaddr & 7) != 0) if ((vaddr & 7) != 0)
SignalExceptionAddressLoad(); SignalExceptionAddressLoad();
else else
{ {
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) unsigned64 memval;
{ AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL);
uword64 memval = 0; LoadMemory(&memval,0,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
uword64 memval1 = 0; COP_LD(((instruction_0 >> 26) & 0x3),FT,memval);;
uword64 mask = 0x7;
unsigned int shift = 4;
unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0);
unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0);
unsigned int byte UNUSED;
LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
}
}
} }
} }
@ -4747,32 +4734,22 @@
*tx19: *tx19:
// end-sanitize-tx19 // end-sanitize-tx19
{ {
unsigned32 instruction = instruction_0; address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
signed_word offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16);
int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
{
address_word vaddr = ((uword64)op1 + offset);
address_word paddr;
int uncached; int uncached;
if ((vaddr & 7) != 0) if ((vaddr & 7) != 0)
SignalExceptionAddressStore(); SignalExceptionAddressStore();
else else
{ {
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) address_word paddr;
{ unsigned64 memval;
uword64 memval = 0; AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
uword64 memval1 = 0; memval = (unsigned64) COP_SD(((instruction_0 >> 26) & 0x3),FT);
memval = (uword64)COP_SD(((instruction >> 26) & 0x3),destreg); StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,0,paddr,vaddr,isREAL);
{
StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
}
}
}
} }
} }
010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
*mipsIV: *mipsIV:
// start-sanitize-vr5400 // start-sanitize-vr5400