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RISC-V: xtheadfmemidx: Use fp register in mnemonics
Although the encoding for scalar and fp registers is identical,
we should follow common pratice and use fp register names
when referencing fp registers.
The xtheadmemidx extension consists of indirect load/store instructions
which all load to or store from fp registers.
Let's use fp register names in this case and adjust the test cases
accordingly.
gas/
* testsuite/gas/riscv/x-thead-fmemidx-fail.l: Updated since rd need to
be float register.
* testsuite/gas/riscv/x-thead-fmemidx-fail.s: Likewise.
* testsuite/gas/riscv/x-thead-fmemidx.d: Likewise.
* testsuite/gas/riscv/x-thead-fmemidx.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Updated since rd need to be float register.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:
Christoph Müllner
committed by
Nelson Chu
Nelson Chu
parent
1db13039a7
commit
a8d181c0fd
@ -1,4 +1,5 @@
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.*: Assembler messages:
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.*: Error: illegal operands `th.flrd a0,a1,a2,0'
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.*: Error: improper immediate value \(18446744073709551615\)
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.*: Error: improper immediate value \(4\)
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.*: Error: improper immediate value \(18446744073709551615\)
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@ -1,17 +1,18 @@
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target:
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th.flrd a0, a1, a2, -1
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th.flrd a0, a1, a2, 4
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th.flrw a0, a1, a2, -1
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th.flrw a0, a1, a2, 4
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th.flurd a0, a1, a2, -1
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th.flurd a0, a1, a2, 4
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th.flurw a0, a1, a2, -1
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th.flurw a0, a1, a2, 4
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th.fsrd a0, a1, a2, -1
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th.fsrd a0, a1, a2, 4
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th.fsrw a0, a1, a2, -1
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th.fsrw a0, a1, a2, 4
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th.fsurd a0, a1, a2, -1
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th.fsurd a0, a1, a2, 4
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th.fsurw a0, a1, a2, -1
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th.fsurw a0, a1, a2, 4
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th.flrd a0, a1, a2, 0
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th.flrd fa0, a1, a2, -1
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th.flrd fa0, a1, a2, 4
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th.flrw fa0, a1, a2, -1
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th.flrw fa0, a1, a2, 4
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th.flurd fa0, a1, a2, -1
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th.flurd fa0, a1, a2, 4
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th.flurw fa0, a1, a2, -1
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th.flurw fa0, a1, a2, 4
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th.fsrd fa0, a1, a2, -1
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th.fsrd fa0, a1, a2, 4
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th.fsrw fa0, a1, a2, -1
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th.fsrw fa0, a1, a2, 4
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th.fsurd fa0, a1, a2, -1
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th.fsurd fa0, a1, a2, 4
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th.fsurw fa0, a1, a2, -1
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th.fsurw fa0, a1, a2, 4
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@ -7,19 +7,19 @@
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+60c5e50b[ ]+th.flrd[ ]+a0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+66c5e50b[ ]+th.flrd[ ]+a0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+40c5e50b[ ]+th.flrw[ ]+a0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+46c5e50b[ ]+th.flrw[ ]+a0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+70c5e50b[ ]+th.flurd[ ]+a0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+76c5e50b[ ]+th.flurd[ ]+a0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+50c5e50b[ ]+th.flurw[ ]+a0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+56c5e50b[ ]+th.flurw[ ]+a0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+60c5f50b[ ]+th.fsrd[ ]+a0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+66c5f50b[ ]+th.fsrd[ ]+a0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+40c5f50b[ ]+th.fsrw[ ]+a0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+46c5f50b[ ]+th.fsrw[ ]+a0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+70c5f50b[ ]+th.fsurd[ ]+a0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+76c5f50b[ ]+th.fsurd[ ]+a0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+50c5f50b[ ]+th.fsurw[ ]+a0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+56c5f50b[ ]+th.fsurw[ ]+a0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+60c5e50b[ ]+th.flrd[ ]+fa0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+66c5e50b[ ]+th.flrd[ ]+fa0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+40c5e50b[ ]+th.flrw[ ]+fa0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+46c5e50b[ ]+th.flrw[ ]+fa0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+70c5e50b[ ]+th.flurd[ ]+fa0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+76c5e50b[ ]+th.flurd[ ]+fa0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+50c5e50b[ ]+th.flurw[ ]+fa0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+56c5e50b[ ]+th.flurw[ ]+fa0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+60c5f50b[ ]+th.fsrd[ ]+fa0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+66c5f50b[ ]+th.fsrd[ ]+fa0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+40c5f50b[ ]+th.fsrw[ ]+fa0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+46c5f50b[ ]+th.fsrw[ ]+fa0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+70c5f50b[ ]+th.fsurd[ ]+fa0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+76c5f50b[ ]+th.fsurd[ ]+fa0,a1,a2,3
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[ ]+[0-9a-f]+:[ ]+50c5f50b[ ]+th.fsurw[ ]+fa0,a1,a2,0
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[ ]+[0-9a-f]+:[ ]+56c5f50b[ ]+th.fsurw[ ]+fa0,a1,a2,3
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@ -1,17 +1,17 @@
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target:
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th.flrd a0, a1, a2, 0
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th.flrd a0, a1, a2, 3
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th.flrw a0, a1, a2, 0
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th.flrw a0, a1, a2, 3
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th.flurd a0, a1, a2, 0
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th.flurd a0, a1, a2, 3
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th.flurw a0, a1, a2, 0
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th.flurw a0, a1, a2, 3
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th.fsrd a0, a1, a2, 0
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th.fsrd a0, a1, a2, 3
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th.fsrw a0, a1, a2, 0
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th.fsrw a0, a1, a2, 3
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th.fsurd a0, a1, a2, 0
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th.fsurd a0, a1, a2, 3
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th.fsurw a0, a1, a2, 0
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th.fsurw a0, a1, a2, 3
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th.flrd fa0, a1, a2, 0
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th.flrd fa0, a1, a2, 3
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th.flrw fa0, a1, a2, 0
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th.flrw fa0, a1, a2, 3
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th.flurd fa0, a1, a2, 0
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th.flurd fa0, a1, a2, 3
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th.flurw fa0, a1, a2, 0
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th.flurw fa0, a1, a2, 3
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th.fsrd fa0, a1, a2, 0
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th.fsrd fa0, a1, a2, 3
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th.fsrw fa0, a1, a2, 0
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th.fsrw fa0, a1, a2, 3
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th.fsurd fa0, a1, a2, 0
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th.fsurd fa0, a1, a2, 3
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th.fsurw fa0, a1, a2, 0
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th.fsurw fa0, a1, a2, 3
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@ -1922,14 +1922,14 @@ const struct riscv_opcode riscv_opcodes[] =
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{"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0},
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/* Vendor-specific (T-Head) XTheadFMemIdx instructions. */
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{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLRD, MASK_TH_FLRD, match_opcode, 0},
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{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLRW, MASK_TH_FLRW, match_opcode, 0},
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{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0},
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{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0},
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{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSRD, MASK_TH_FSRD, match_opcode, 0},
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{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSRW, MASK_TH_FSRW, match_opcode, 0},
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{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0},
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{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0},
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{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLRD, MASK_TH_FLRD, match_opcode, 0},
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{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLRW, MASK_TH_FLRW, match_opcode, 0},
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{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0},
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{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0},
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{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSRD, MASK_TH_FSRD, match_opcode, 0},
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{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSRW, MASK_TH_FSRW, match_opcode, 0},
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{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0},
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{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0},
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/* Vendor-specific (T-Head) XTheadMemIdx instructions. */
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{"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, 0},
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