mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-06-25 21:41:47 +08:00
Correctly emit lo16 relocs for elf-dlx target, fixing bogus range checking bug.
This commit is contained in:
@ -1,3 +1,13 @@
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2004-04-01 Dave Korn <dk@artimi.com>
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* config/tc-dlx.c (md_assemble): set fx_no_overflow flag for
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hi16 and lo16 fixS structs.
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(md_assemble): generate bit_fixS for RELOC_DLX_LO16 in
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exactly the same way as for RELOC_DLX_REL16.
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(machine_ip): properly respect LO flag in the_insn and
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output RELOC_DLX_LO16 rather than RELOC_DLX_16.
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(md_apply_fix3): apply RELOC_DLX_LO16.
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2004-03-30 Stan Shebs <shebs@apple.com>
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2004-03-30 Stan Shebs <shebs@apple.com>
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Remove long-obsolete MPW support.
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Remove long-obsolete MPW support.
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@ -1,5 +1,5 @@
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/* tc-ldx.c -- Assemble for the DLX
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/* tc-ldx.c -- Assemble for the DLX
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Copyright 2002, 2003 Free Software Foundation, Inc.
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Copyright 2002, 2003, 2004 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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This file is part of GAS, the GNU Assembler.
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@ -397,6 +397,18 @@ md_assemble (str)
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the_insn.size, & the_insn.exp, the_insn.pcrel,
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the_insn.size, & the_insn.exp, the_insn.pcrel,
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the_insn.reloc);
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the_insn.reloc);
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/* Turn off complaints that the addend is
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too large for things like foo+100000@ha. */
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switch (the_insn.reloc)
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{
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case RELOC_DLX_HI16:
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case RELOC_DLX_LO16:
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fixP->fx_no_overflow = 1;
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break;
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default:
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break;
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}
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switch (fixP->fx_r_type)
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switch (fixP->fx_r_type)
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{
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{
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case RELOC_DLX_REL26:
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case RELOC_DLX_REL26:
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@ -410,6 +422,7 @@ md_assemble (str)
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bitP->fx_bit_add = 0x03FFFFFF;
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bitP->fx_bit_add = 0x03FFFFFF;
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fixP->fx_bit_fixP = bitP;
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fixP->fx_bit_fixP = bitP;
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break;
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break;
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case RELOC_DLX_LO16:
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case RELOC_DLX_REL16:
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case RELOC_DLX_REL16:
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bitP = malloc (sizeof (bit_fixS));
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bitP = malloc (sizeof (bit_fixS));
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bitP->fx_bit_size = 16;
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bitP->fx_bit_size = 16;
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@ -955,7 +968,8 @@ machine_ip (str)
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continue;
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continue;
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}
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}
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the_insn.reloc = (the_insn.HI) ? RELOC_DLX_HI16 : RELOC_DLX_16;
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the_insn.reloc = (the_insn.HI) ? RELOC_DLX_HI16
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: (the_insn.LO ? RELOC_DLX_LO16 : RELOC_DLX_16);
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the_insn.reloc_offset = 2;
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the_insn.reloc_offset = 2;
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the_insn.size = 2;
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the_insn.size = 2;
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the_insn.pcrel = 0;
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the_insn.pcrel = 0;
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@ -1164,6 +1178,7 @@ md_apply_fix3 (fixP, valP, seg)
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switch (fixP->fx_r_type)
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switch (fixP->fx_r_type)
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{
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{
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case RELOC_DLX_LO16:
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case RELOC_DLX_REL16:
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case RELOC_DLX_REL16:
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if (fixP->fx_bit_fixP != (bit_fixS *) NULL)
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if (fixP->fx_bit_fixP != (bit_fixS *) NULL)
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{
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{
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@ -1,3 +1,14 @@
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2004-04-01 Dave Korn <dk@artimi.com>
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* gas/dlx/alltests.exp: Execute new lohi test.
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* gas/dlx/lohi.s: New test for spurious lo16/hi16
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reloc overflow checking.
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* gas/dlx/lohi.d: New file: expected output.
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* gas/dlx/lhi.d: Updated to properly expect lo16
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relocations where asked for.
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* gas/dlx/itype.d: Likewise.
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* gas/dlx/lhi.d: Corrected cut+paste error in test name.
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2004-03-30 Stan Shebs <shebs@apple.com>
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2004-03-30 Stan Shebs <shebs@apple.com>
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* gas/macros/macros.exp: Remove mention of MPW config.
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* gas/macros/macros.exp: Remove mention of MPW config.
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@ -5,6 +5,7 @@ if [istarget dlx*-*-*] {
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run_dump_test "itype"
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run_dump_test "itype"
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run_dump_test "lhi"
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run_dump_test "lhi"
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run_dump_test "load"
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run_dump_test "load"
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run_dump_test "lohi"
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run_dump_test "rtype"
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run_dump_test "rtype"
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run_dump_test "store"
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run_dump_test "store"
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}
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}
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@ -16,7 +16,7 @@ Disassembly of section .text:
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12: R_DLX_RELOC_16 .text
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12: R_DLX_RELOC_16 .text
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14: 35 4c 00 78 ori r12,r10,0x0078
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14: 35 4c 00 78 ori r12,r10,0x0078
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18: 39 af 00 00 xori r15,r13,0x0000
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18: 39 af 00 00 xori r15,r13,0x0000
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1a: R_DLX_RELOC_16 .text
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1a: R_DLX_RELOC_16_LO .text
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1c: da 30 00 1c slli r16,r17,0x001c
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1c: da 30 00 1c slli r16,r17,0x001c
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1e: R_DLX_RELOC_16 .text
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1e: R_DLX_RELOC_16 .text
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20: e2 93 00 0f srai r19,r20,0x000f
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20: e2 93 00 0f srai r19,r20,0x000f
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@ -1,6 +1,6 @@
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#as:
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#as:
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#objdump: -dr
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#objdump: -dr
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#name: itype
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#name: lhi
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.*: +file format .*
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.*: +file format .*
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@ -11,7 +11,7 @@ Disassembly of section .text:
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4: 3c 03 00 00 lhi r3,0x0000
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4: 3c 03 00 00 lhi r3,0x0000
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6: R_DLX_RELOC_16_HI .text
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6: R_DLX_RELOC_16_HI .text
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8: 3c 04 00 00 lhi r4,0x0000
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8: 3c 04 00 00 lhi r4,0x0000
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a: R_DLX_RELOC_16 .text
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a: R_DLX_RELOC_16_LO .text
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c: 3c 04 ff fb lhi r4,0xfffb
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c: 3c 04 ff fb lhi r4,0xfffb
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e: R_DLX_RELOC_16 .text
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e: R_DLX_RELOC_16 .text
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10: 3c 04 00 0c lhi r4,0x000c
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10: 3c 04 00 0c lhi r4,0x000c
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@ -19,5 +19,5 @@ Disassembly of section .text:
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18: 20 04 00 00 addi r4,r0,0x0000
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18: 20 04 00 00 addi r4,r0,0x0000
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1a: R_DLX_RELOC_16_HI .text
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1a: R_DLX_RELOC_16_HI .text
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1c: 34 84 00 18 ori r4,r4,0x0018
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1c: 34 84 00 18 ori r4,r4,0x0018
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1e: R_DLX_RELOC_16 .text
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1e: R_DLX_RELOC_16_LO .text
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20: 20 64 00 00 addi r4,r3,0x0000
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20: 20 64 00 00 addi r4,r3,0x0000
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18
gas/testsuite/gas/dlx/lohi.d
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18
gas/testsuite/gas/dlx/lohi.d
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@ -0,0 +1,18 @@
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#as:
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#objdump: -dr
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#name: lohi
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.*: +file format .*
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Disassembly of section .text:
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00000000 <.text>:
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0: 00 00 00 00 nop
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4: 3c 01 00 03 lhi r1,0x0003
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6: R_DLX_RELOC_16_HI .text
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8: 34 01 0d 44 ori r1,r0,0x0d44
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a: R_DLX_RELOC_16_LO .text
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c: 3c 01 0b eb lhi r1,0x0beb
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e: R_DLX_RELOC_16_HI .text
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10: 34 01 c2 04 ori r1,r0,0xc204
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12: R_DLX_RELOC_16_LO .text
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9
gas/testsuite/gas/dlx/lohi.s
Normal file
9
gas/testsuite/gas/dlx/lohi.s
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@ -0,0 +1,9 @@
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.text
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.align 2
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nop
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.L1:
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lhi r1,%hi(.L1 + 200000)
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ori r1,r0,%lo(.L1 + 200000)
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lhi r1,%hi(.L1 + 200000000)
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ori r1,r0,%lo(.L1 + 200000000)
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.end
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