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gas/
2008-02-13 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (allow_pseudo_reg): New. (parse_real_register): Check for NULL just once. Allow all register table entries when allow_pseudo_reg is non-zero. Don't allow any registers without type when allow_pseudo_reg is zero. (tc_x86_regname_to_dw2regnum): Replace with ... (tc_x86_parse_to_dw2regnum): ... this. (tc_x86_frame_initial_instructions): Adjust for above change. * config/tc-i386.h (tc_regname_to_dw2regnum): Remove. (tc_parse_to_dw2regnum): New. (tc_x86_regname_to_dw2regnum): Replace with ... (tc_x86_parse_to_dw2regnum): ... this. * dw2gencfi.c (tc_parse_to_dw2regnum): New, broken out of ... (cfi_parse_reg): ... this. Use tc_parse_to_dw2regnum. Adjust error handling. gas/testsuite/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * gas/cfi/cfi-i386.s: Add code testing use of all registers. Fix a few comments. * gas/cfi/cfi-x86_64.s: Likewise. * gas/cfi/cfi-i386.d, gas/cfi/cfi-x86_64.d: Adjust. opcodes/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * i386-gen.c (process_i386_registers): Process new fields. * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to unsigned char. Add dw2_regnum and Dw2Inval. * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo register names. * i386-tbl.h: Re-generate.
This commit is contained in:
Jan Beulich
@ -20,187 +20,206 @@
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// 02110-1301, USA.
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// Make %st first as we test for it.
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st, FloatReg|FloatAcc, 0, 0
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st, FloatReg|FloatAcc, 0, 0, 11, 33
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// 8 bit regs
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al, Reg8|Acc|Byte, 0, 0
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cl, Reg8|ShiftCount, 0, 1
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dl, Reg8, 0, 2
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bl, Reg8, 0, 3
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ah, Reg8, 0, 4
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ch, Reg8, 0, 5
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dh, Reg8, 0, 6
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bh, Reg8, 0, 7
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axl, Reg8|Acc|Byte, RegRex64, 0
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cxl, Reg8, RegRex64, 1
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dxl, Reg8, RegRex64, 2
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bxl, Reg8, RegRex64, 3
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spl, Reg8, RegRex64, 4
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bpl, Reg8, RegRex64, 5
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sil, Reg8, RegRex64, 6
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dil, Reg8, RegRex64, 7
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r8b, Reg8, RegRex|RegRex64, 0
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r9b, Reg8, RegRex|RegRex64, 1
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r10b, Reg8, RegRex|RegRex64, 2
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r11b, Reg8, RegRex|RegRex64, 3
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r12b, Reg8, RegRex|RegRex64, 4
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r13b, Reg8, RegRex|RegRex64, 5
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r14b, Reg8, RegRex|RegRex64, 6
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r15b, Reg8, RegRex|RegRex64, 7
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al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
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cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
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dl, Reg8, 0, 2, Dw2Inval, Dw2Inval
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bl, Reg8, 0, 3, Dw2Inval, Dw2Inval
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ah, Reg8, 0, 4, Dw2Inval, Dw2Inval
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ch, Reg8, 0, 5, Dw2Inval, Dw2Inval
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dh, Reg8, 0, 6, Dw2Inval, Dw2Inval
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bh, Reg8, 0, 7, Dw2Inval, Dw2Inval
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axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
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cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval
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dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval
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bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval
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spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval
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bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval
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sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval
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dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval
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r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
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r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
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r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
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r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
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r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
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r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
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r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
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r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
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// 16 bit regs
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ax, Reg16|Acc|Word, 0, 0
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cx, Reg16, 0, 1
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dx, Reg16|InOutPortReg, 0, 2
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bx, Reg16|BaseIndex, 0, 3
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sp, Reg16, 0, 4
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bp, Reg16|BaseIndex, 0, 5
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si, Reg16|BaseIndex, 0, 6
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di, Reg16|BaseIndex, 0, 7
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r8w, Reg16, RegRex, 0
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r9w, Reg16, RegRex, 1
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r10w, Reg16, RegRex, 2
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r11w, Reg16, RegRex, 3
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r12w, Reg16, RegRex, 4
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r13w, Reg16, RegRex, 5
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r14w, Reg16, RegRex, 6
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r15w, Reg16, RegRex, 7
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ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
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cx, Reg16, 0, 1, Dw2Inval, Dw2Inval
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dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
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bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
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sp, Reg16, 0, 4, Dw2Inval, Dw2Inval
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bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
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si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
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di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
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r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval
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r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval
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r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval
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r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval
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r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval
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r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval
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r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval
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r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval
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// 32 bit regs
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eax, Reg32|BaseIndex|Acc|Dword, 0, 0
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ecx, Reg32|BaseIndex, 0, 1
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edx, Reg32|BaseIndex, 0, 2
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ebx, Reg32|BaseIndex, 0, 3
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esp, Reg32, 0, 4
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ebp, Reg32|BaseIndex, 0, 5
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esi, Reg32|BaseIndex, 0, 6
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edi, Reg32|BaseIndex, 0, 7
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r8d, Reg32|BaseIndex, RegRex, 0
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r9d, Reg32|BaseIndex, RegRex, 1
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r10d, Reg32|BaseIndex, RegRex, 2
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r11d, Reg32|BaseIndex, RegRex, 3
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r12d, Reg32|BaseIndex, RegRex, 4
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r13d, Reg32|BaseIndex, RegRex, 5
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r14d, Reg32|BaseIndex, RegRex, 6
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r15d, Reg32|BaseIndex, RegRex, 7
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rax, Reg64|BaseIndex|Acc|Qword, 0, 0
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rcx, Reg64|BaseIndex, 0, 1
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rdx, Reg64|BaseIndex, 0, 2
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rbx, Reg64|BaseIndex, 0, 3
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rsp, Reg64, 0, 4
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rbp, Reg64|BaseIndex, 0, 5
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rsi, Reg64|BaseIndex, 0, 6
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rdi, Reg64|BaseIndex, 0, 7
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r8, Reg64|BaseIndex, RegRex, 0
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r9, Reg64|BaseIndex, RegRex, 1
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r10, Reg64|BaseIndex, RegRex, 2
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r11, Reg64|BaseIndex, RegRex, 3
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r12, Reg64|BaseIndex, RegRex, 4
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r13, Reg64|BaseIndex, RegRex, 5
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r14, Reg64|BaseIndex, RegRex, 6
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r15, Reg64|BaseIndex, RegRex, 7
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eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval
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ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval
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edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval
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ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval
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esp, Reg32, 0, 4, 4, Dw2Inval
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ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval
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esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval
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edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval
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r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
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r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
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r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
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r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
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r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
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r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
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r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
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r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
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rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0
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rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2
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rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1
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rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3
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rsp, Reg64, 0, 4, Dw2Inval, 7
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rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6
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rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4
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rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5
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r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8
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r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9
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r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10
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r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11
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r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12
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r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13
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r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14
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r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15
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// Segment registers.
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es, SReg2, 0, 0
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cs, SReg2, 0, 1
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ss, SReg2, 0, 2
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ds, SReg2, 0, 3
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fs, SReg3, 0, 4
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gs, SReg3, 0, 5
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es, SReg2, 0, 0, 40, 50
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cs, SReg2, 0, 1, 41, 51
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ss, SReg2, 0, 2, 42, 52
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ds, SReg2, 0, 3, 43, 53
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fs, SReg3, 0, 4, 44, 54
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gs, SReg3, 0, 5, 45, 55
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// Control registers.
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cr0, Control, 0, 0
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cr1, Control, 0, 1
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cr2, Control, 0, 2
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cr3, Control, 0, 3
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cr4, Control, 0, 4
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cr5, Control, 0, 5
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cr6, Control, 0, 6
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cr7, Control, 0, 7
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cr8, Control, RegRex, 0
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cr9, Control, RegRex, 1
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cr10, Control, RegRex, 2
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cr11, Control, RegRex, 3
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cr12, Control, RegRex, 4
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cr13, Control, RegRex, 5
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cr14, Control, RegRex, 6
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cr15, Control, RegRex, 7
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cr0, Control, 0, 0, Dw2Inval, Dw2Inval
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cr1, Control, 0, 1, Dw2Inval, Dw2Inval
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cr2, Control, 0, 2, Dw2Inval, Dw2Inval
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cr3, Control, 0, 3, Dw2Inval, Dw2Inval
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cr4, Control, 0, 4, Dw2Inval, Dw2Inval
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cr5, Control, 0, 5, Dw2Inval, Dw2Inval
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cr6, Control, 0, 6, Dw2Inval, Dw2Inval
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cr7, Control, 0, 7, Dw2Inval, Dw2Inval
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cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval
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cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval
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cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval
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cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval
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cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval
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cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval
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cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval
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cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval
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// Debug registers.
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db0, Debug, 0, 0
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db1, Debug, 0, 1
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db2, Debug, 0, 2
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db3, Debug, 0, 3
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db4, Debug, 0, 4
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db5, Debug, 0, 5
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db6, Debug, 0, 6
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db7, Debug, 0, 7
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db8, Debug, RegRex, 0
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db9, Debug, RegRex, 1
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db10, Debug, RegRex, 2
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db11, Debug, RegRex, 3
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db12, Debug, RegRex, 4
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db13, Debug, RegRex, 5
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db14, Debug, RegRex, 6
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db15, Debug, RegRex, 7
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dr0, Debug, 0, 0
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dr1, Debug, 0, 1
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dr2, Debug, 0, 2
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dr3, Debug, 0, 3
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dr4, Debug, 0, 4
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dr5, Debug, 0, 5
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dr6, Debug, 0, 6
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dr7, Debug, 0, 7
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dr8, Debug, RegRex, 0
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dr9, Debug, RegRex, 1
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dr10, Debug, RegRex, 2
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dr11, Debug, RegRex, 3
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dr12, Debug, RegRex, 4
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dr13, Debug, RegRex, 5
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dr14, Debug, RegRex, 6
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dr15, Debug, RegRex, 7
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db0, Debug, 0, 0, Dw2Inval, Dw2Inval
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db1, Debug, 0, 1, Dw2Inval, Dw2Inval
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db2, Debug, 0, 2, Dw2Inval, Dw2Inval
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db3, Debug, 0, 3, Dw2Inval, Dw2Inval
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db4, Debug, 0, 4, Dw2Inval, Dw2Inval
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db5, Debug, 0, 5, Dw2Inval, Dw2Inval
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db6, Debug, 0, 6, Dw2Inval, Dw2Inval
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db7, Debug, 0, 7, Dw2Inval, Dw2Inval
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db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
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db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
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db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
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db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
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db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
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db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
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db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
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db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
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dr0, Debug, 0, 0, Dw2Inval, Dw2Inval
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dr1, Debug, 0, 1, Dw2Inval, Dw2Inval
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dr2, Debug, 0, 2, Dw2Inval, Dw2Inval
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dr3, Debug, 0, 3, Dw2Inval, Dw2Inval
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dr4, Debug, 0, 4, Dw2Inval, Dw2Inval
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dr5, Debug, 0, 5, Dw2Inval, Dw2Inval
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dr6, Debug, 0, 6, Dw2Inval, Dw2Inval
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dr7, Debug, 0, 7, Dw2Inval, Dw2Inval
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dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
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dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
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dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
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dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
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dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
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dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
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dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
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dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
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// Test registers.
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tr0, Test, 0, 0
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tr1, Test, 0, 1
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tr2, Test, 0, 2
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tr3, Test, 0, 3
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tr4, Test, 0, 4
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tr5, Test, 0, 5
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tr6, Test, 0, 6
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tr7, Test, 0, 7
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tr0, Test, 0, 0, Dw2Inval, Dw2Inval
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tr1, Test, 0, 1, Dw2Inval, Dw2Inval
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tr2, Test, 0, 2, Dw2Inval, Dw2Inval
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tr3, Test, 0, 3, Dw2Inval, Dw2Inval
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tr4, Test, 0, 4, Dw2Inval, Dw2Inval
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tr5, Test, 0, 5, Dw2Inval, Dw2Inval
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tr6, Test, 0, 6, Dw2Inval, Dw2Inval
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tr7, Test, 0, 7, Dw2Inval, Dw2Inval
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// MMX and simd registers.
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mm0, RegMMX, 0, 0
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mm1, RegMMX, 0, 1
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mm2, RegMMX, 0, 2
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mm3, RegMMX, 0, 3
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mm4, RegMMX, 0, 4
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mm5, RegMMX, 0, 5
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mm6, RegMMX, 0, 6
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mm7, RegMMX, 0, 7
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xmm0, RegXMM, 0, 0
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xmm1, RegXMM, 0, 1
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xmm2, RegXMM, 0, 2
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xmm3, RegXMM, 0, 3
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xmm4, RegXMM, 0, 4
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xmm5, RegXMM, 0, 5
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xmm6, RegXMM, 0, 6
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xmm7, RegXMM, 0, 7
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xmm8, RegXMM, RegRex, 0
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xmm9, RegXMM, RegRex, 1
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xmm10, RegXMM, RegRex, 2
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xmm11, RegXMM, RegRex, 3
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xmm12, RegXMM, RegRex, 4
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xmm13, RegXMM, RegRex, 5
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xmm14, RegXMM, RegRex, 6
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xmm15, RegXMM, RegRex, 7
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mm0, RegMMX, 0, 0, 29, 41
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mm1, RegMMX, 0, 1, 30, 42
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mm2, RegMMX, 0, 2, 31, 43
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mm3, RegMMX, 0, 3, 32, 44
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mm4, RegMMX, 0, 4, 33, 45
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mm5, RegMMX, 0, 5, 34, 46
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mm6, RegMMX, 0, 6, 35, 47
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mm7, RegMMX, 0, 7, 36, 48
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xmm0, RegXMM, 0, 0, 21, 17
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xmm1, RegXMM, 0, 1, 22, 18
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xmm2, RegXMM, 0, 2, 23, 19
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xmm3, RegXMM, 0, 3, 24, 20
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xmm4, RegXMM, 0, 4, 25, 21
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xmm5, RegXMM, 0, 5, 26, 22
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xmm6, RegXMM, 0, 6, 27, 23
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xmm7, RegXMM, 0, 7, 28, 24
|
||||
xmm8, RegXMM, RegRex, 0, Dw2Inval, 25
|
||||
xmm9, RegXMM, RegRex, 1, Dw2Inval, 26
|
||||
xmm10, RegXMM, RegRex, 2, Dw2Inval, 27
|
||||
xmm11, RegXMM, RegRex, 3, Dw2Inval, 28
|
||||
xmm12, RegXMM, RegRex, 4, Dw2Inval, 29
|
||||
xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
|
||||
xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
|
||||
xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
|
||||
// No type will make these registers rejected for all purposes except
|
||||
// for addressing. This saves creating one extra type for RIP/EIP.
|
||||
rip, BaseIndex, RegRex64, RegRip
|
||||
eip, BaseIndex, RegRex64, RegEip
|
||||
rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
|
||||
eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
|
||||
// No type will make these registers rejected for all purposes except
|
||||
// for addressing.
|
||||
eiz, BaseIndex, 0, RegEiz
|
||||
riz, BaseIndex, 0, RegRiz
|
||||
eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
|
||||
riz, BaseIndex, 0, RegRiz, Dw2Inval, Dw2Inval
|
||||
// fp regs.
|
||||
st(0), FloatReg|FloatAcc, 0, 0
|
||||
st(1), FloatReg, 0, 1
|
||||
st(2), FloatReg, 0, 2
|
||||
st(3), FloatReg, 0, 3
|
||||
st(4), FloatReg, 0, 4
|
||||
st(5), FloatReg, 0, 5
|
||||
st(6), FloatReg, 0, 6
|
||||
st(7), FloatReg, 0, 7
|
||||
st(0), FloatReg|FloatAcc, 0, 0, 11, 33
|
||||
st(1), FloatReg, 0, 1, 12, 34
|
||||
st(2), FloatReg, 0, 2, 13, 35
|
||||
st(3), FloatReg, 0, 3, 14, 36
|
||||
st(4), FloatReg, 0, 4, 15, 37
|
||||
st(5), FloatReg, 0, 5, 16, 38
|
||||
st(6), FloatReg, 0, 6, 17, 39
|
||||
st(7), FloatReg, 0, 7, 18, 40
|
||||
// Pseudo-register names only used in .cfi_* directives
|
||||
eflags, 0, 0, 0, 9, 49
|
||||
rflags, 0, 0, 0, Dw2Inval, 49
|
||||
fs.base, 0, 0, 0, Dw2Inval, 58
|
||||
gs.base, 0, 0, 0, Dw2Inval, 59
|
||||
tr, 0, 0, 0, 48, 62
|
||||
ldtr, 0, 0, 0, 49, 63
|
||||
// st0...7 for backward compatibility
|
||||
st0, 0, 0, 0, 11, 33
|
||||
st1, 0, 0, 1, 12, 34
|
||||
st2, 0, 0, 2, 13, 35
|
||||
st3, 0, 0, 3, 14, 36
|
||||
st4, 0, 0, 4, 15, 37
|
||||
st5, 0, 0, 5, 16, 38
|
||||
st6, 0, 0, 6, 17, 39
|
||||
st7, 0, 0, 7, 18, 40
|
||||
fcw, 0, 0, 0, 37, 65
|
||||
fsw, 0, 0, 0, 38, 66
|
||||
mxcsr, 0, 0, 0, 39, 64
|
||||
|
||||
Reference in New Issue
Block a user