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sim-main.h: Re-arange r5900 registers so that they have their own
little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
This commit is contained in:
Andrew Cagney
@ -305,6 +305,7 @@ sim_open (kind, cb, abfd, argv)
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/* For compatibility with the old code - under this (at level one)
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are the kernel spaces K0 & K1. Both of these map to a single
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smaller sub region */
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sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
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sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
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K1BASE, K0SIZE,
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MEM_SIZE, /* actual size */
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@ -367,7 +368,10 @@ sim_open (kind, cb, abfd, argv)
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cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
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else if ((rn >= 33) && (rn <= 37))
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cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
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else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))
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else if ((rn == SRIDX)
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|| (rn == FCR0IDX)
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|| (rn == FCR31IDX)
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|| ((rn >= 72) && (rn <= 89)))
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cpu->register_widths[rn] = 32;
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else
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cpu->register_widths[rn] = 0;
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@ -605,7 +609,31 @@ sim_store_register (sd,rn,memory,length)
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register number is for the architecture being simulated. */
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if (cpu->register_widths[rn] == 0)
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sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
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{
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sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
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return 0;
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}
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/* start-sanitize-r5900 */
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if (rn >= 90 && rn < 90 + 32)
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{
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GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory);
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return 8;
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}
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switch (rn)
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{
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case REGISTER_SA:
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SA = T2H_8(*(unsigned64*)memory);
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return 8;
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case 122: /* FIXME */
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LO1 = T2H_8(*(unsigned64*)memory);
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return 8;
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case 123: /* FIXME */
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HI1 = T2H_8(*(unsigned64*)memory);
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return 8;
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}
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/* end-sanitize-r5900 */
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/* start-sanitize-sky */
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#ifdef TARGET_SKY
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else if( rn > NUM_R5900_REGS ) {
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@ -628,25 +656,31 @@ sim_store_register (sd,rn,memory,length)
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}
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#endif
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/* end-sanitize-sky */
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/* start-sanitize-r5900 */
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else if (rn == REGISTER_SA)
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SA = T2H_8(*(unsigned64*)memory);
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else if (rn > LAST_EMBED_REGNUM)
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cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(unsigned64*)memory);
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/* end-sanitize-r5900 */
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else if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
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if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
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{
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if (cpu->register_widths[rn] == 32)
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cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
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{
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cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
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return 4;
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}
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else
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cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
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{
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cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
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return 8;
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}
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}
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else if (cpu->register_widths[rn] == 32)
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cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
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else
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cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
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return -1;
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if (cpu->register_widths[rn] == 32)
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{
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cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
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return 4;
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}
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else
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{
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cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
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return 8;
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}
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}
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int
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@ -664,10 +698,34 @@ sim_fetch_register (sd,rn,memory,length)
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#endif /* DEBUG */
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if (cpu->register_widths[rn] == 0)
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sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn);
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{
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sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
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return 0;
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}
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/* start-sanitize-r5900 */
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if (rn >= 90 && rn < 90 + 32)
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{
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*(unsigned64*)memory = GPR1[rn - 90];
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return 8;
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}
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switch (rn)
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{
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case REGISTER_SA:
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*((unsigned64*)memory) = H2T_8(SA);
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return 8;
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case 122: /* FIXME */
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*((unsigned64*)memory) = H2T_8(LO1);
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return 8;
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case 123: /* FIXME */
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*((unsigned64*)memory) = H2T_8(HI1);
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return 8;
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}
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/* end-sanitize-r5900 */
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/* start-sanitize-sky */
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#ifdef TARGET_SKY
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else if( rn > NUM_R5900_REGS ) {
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if( rn > NUM_R5900_REGS ) {
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rn = rn - NUM_R5900_REGS;
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if( rn < 16 )
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@ -684,28 +742,37 @@ sim_fetch_register (sd,rn,memory,length)
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else
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sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
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}
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return -1;
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}
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#endif
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/* end-sanitize-sky */
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/* start-sanitize-r5900 */
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else if (rn == REGISTER_SA)
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*((unsigned64*)memory) = H2T_8(SA);
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else if (rn > LAST_EMBED_REGNUM)
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*((unsigned64*)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]);
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/* end-sanitize-r5900 */
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else if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
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/* Any floating point register */
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if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
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{
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if (cpu->register_widths[rn] == 32)
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*(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
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{
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*(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
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return 4;
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}
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else
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*(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
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{
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*(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
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return 8;
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}
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}
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else if (cpu->register_widths[rn] == 32)
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*(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
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else /* 64bit register */
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*(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
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return -1;
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if (cpu->register_widths[rn] == 32)
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{
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*(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
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return 4;
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}
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else
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{
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*(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
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return 8;
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}
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}
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@ -2856,6 +2923,142 @@ SquareRoot(op,fmt)
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return(result);
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}
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uword64
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Max (uword64 op1,
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uword64 op2,
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FP_formats fmt)
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{
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int cmp;
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unsigned64 result;
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#ifdef DEBUG
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printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
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#endif /* DEBUG */
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/* The registers must specify FPRs valid for operands of type
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"fmt". If they are not valid, the result is undefined. */
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/* The format type should already have been checked: */
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switch (fmt)
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{
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case fmt_single:
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{
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sim_fpu wop1;
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sim_fpu wop2;
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sim_fpu_32to (&wop1, op1);
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sim_fpu_32to (&wop2, op2);
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cmp = sim_fpu_cmp (&wop1, &wop2);
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break;
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}
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case fmt_double:
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{
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sim_fpu wop1;
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sim_fpu wop2;
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sim_fpu_64to (&wop1, op1);
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sim_fpu_64to (&wop2, op2);
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cmp = sim_fpu_cmp (&wop1, &wop2);
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break;
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}
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default:
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fprintf (stderr, "Bad switch\n");
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abort ();
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}
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switch (cmp)
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{
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case SIM_FPU_IS_SNAN:
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case SIM_FPU_IS_QNAN:
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result = op1;
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case SIM_FPU_IS_NINF:
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case SIM_FPU_IS_NNUMBER:
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case SIM_FPU_IS_NDENORM:
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case SIM_FPU_IS_NZERO:
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result = op2; /* op1 - op2 < 0 */
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case SIM_FPU_IS_PINF:
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case SIM_FPU_IS_PNUMBER:
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case SIM_FPU_IS_PDENORM:
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case SIM_FPU_IS_PZERO:
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result = op1; /* op1 - op2 > 0 */
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default:
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fprintf (stderr, "Bad switch\n");
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abort ();
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}
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#ifdef DEBUG
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printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
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#endif /* DEBUG */
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return(result);
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}
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uword64
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Min (uword64 op1,
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uword64 op2,
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FP_formats fmt)
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{
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int cmp;
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unsigned64 result;
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#ifdef DEBUG
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printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
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#endif /* DEBUG */
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/* The registers must specify FPRs valid for operands of type
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"fmt". If they are not valid, the result is undefined. */
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/* The format type should already have been checked: */
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switch (fmt)
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{
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case fmt_single:
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{
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sim_fpu wop1;
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sim_fpu wop2;
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sim_fpu_32to (&wop1, op1);
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sim_fpu_32to (&wop2, op2);
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cmp = sim_fpu_cmp (&wop1, &wop2);
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break;
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}
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case fmt_double:
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{
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sim_fpu wop1;
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sim_fpu wop2;
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sim_fpu_64to (&wop1, op1);
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sim_fpu_64to (&wop2, op2);
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cmp = sim_fpu_cmp (&wop1, &wop2);
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break;
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}
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default:
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fprintf (stderr, "Bad switch\n");
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abort ();
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}
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switch (cmp)
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{
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case SIM_FPU_IS_SNAN:
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case SIM_FPU_IS_QNAN:
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result = op1;
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case SIM_FPU_IS_NINF:
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case SIM_FPU_IS_NNUMBER:
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case SIM_FPU_IS_NDENORM:
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case SIM_FPU_IS_NZERO:
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result = op1; /* op1 - op2 < 0 */
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case SIM_FPU_IS_PINF:
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case SIM_FPU_IS_PNUMBER:
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case SIM_FPU_IS_PDENORM:
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case SIM_FPU_IS_PZERO:
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result = op2; /* op1 - op2 > 0 */
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default:
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fprintf (stderr, "Bad switch\n");
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abort ();
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}
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#ifdef DEBUG
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printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
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#endif /* DEBUG */
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return(result);
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}
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uword64
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convert (SIM_DESC sd,
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sim_cpu *cpu,
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