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* config/tc-mips.c (COP_INSN): Change logic to always return false

Browse Source 
for FP instructions.

testsuite/
	* gas/mips/mips1-fp.s, testsuite/gas/mips/mips1-fp.d,
	testsuite/gas/mips/mips1-fp.l: New tests.
	* gas/mips/mips.exp: Run them.
This commit is contained in:
Adam Nemet
2008-11-06 19:49:26 +00:00
parent 5fb8dac153
commit a242dc0d23
7 changed files with 39 additions and 4 deletions

5
gas/ChangeLog

@ -1,3 +1,8 @@
2008-11-06 Adam Nemet <anemet@caviumnetworks.com>
* config/tc-mips.c (COP_INSN): Change logic to always return false
for FP instructions.
2008-11-06 Chao-ying Fu <fu@mips.com> 2008-11-06 Chao-ying Fu <fu@mips.com>
* config/tc-mips.c (validate_mips_insn): Add case '1'. * config/tc-mips.c (validate_mips_insn): Add case '1'.

7
gas/config/tc-mips.c

@ -514,12 +514,11 @@ static int mips_32bitmode = 0;
/* Returns true for a (non floating-point) coprocessor instruction. Reading /* Returns true for a (non floating-point) coprocessor instruction. Reading
or writing the condition code is only possible on the coprocessors and or writing the condition code is only possible on the coprocessors and
these insns are not marked with INSN_COP. Thus for these insns use the these insns are not marked with INSN_COP. Thus for these insns use the
condition-code flags unless this is the floating-point coprocessor. */ condition-code flags. */
#define COP_INSN(PINFO) \ #define COP_INSN(PINFO) \
(PINFO != INSN_MACRO \ (PINFO != INSN_MACRO \
&& (((PINFO) & INSN_COP) \ && ((PINFO) & (FP_S | FP_D)) == 0 \
|| ((PINFO) & (INSN_READ_COND_CODE | INSN_WRITE_COND_CODE) \ && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
&& ((PINFO) & (FP_S | FP_D)) == 0)))
/* MIPS PIC level. */ /* MIPS PIC level. */

6
gas/testsuite/ChangeLog

@ -1,3 +1,9 @@
2008-11-06 Adam Nemet <anemet@caviumnetworks.com>
* gas/mips/mips1-fp.s, testsuite/gas/mips/mips1-fp.d,
testsuite/gas/mips/mips1-fp.l: New tests.
* gas/mips/mips.exp: Run them.
2008-11-06 Chao-ying Fu <fu@mips.com> 2008-11-06 Chao-ying Fu <fu@mips.com>
* gas/mips/mips32-sync.d, gas/mip/mips32-sync.s: New tests. * gas/mips/mips32-sync.d, gas/mip/mips32-sync.s: New tests.

3
gas/testsuite/gas/mips/mips.exp

@ -398,6 +398,9 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "abs" [mips_arch_list_matching mips1] run_dump_test_arches "abs" [mips_arch_list_matching mips1]
run_dump_test_arches "add" [mips_arch_list_matching mips1] run_dump_test_arches "add" [mips_arch_list_matching mips1]
run_dump_test_arches "and" [mips_arch_list_matching mips1] run_dump_test_arches "and" [mips_arch_list_matching mips1]
run_dump_test_arches "mips1-fp" [mips_arch_list_matching mips1]
run_list_test_arches "mips1-fp" "-32 -msoft-float" \
[mips_arch_list_matching mips1]
run_dump_test "break20" run_dump_test "break20"
run_dump_test "trap20" run_dump_test "trap20"

12
gas/testsuite/gas/mips/mips1-fp.d Normal file

@ -0,0 +1,12 @@
#as: -32
#objdump: -M reg-names=numeric -dr
#name: MIPS1 FP instructions
.*: file format .*
Disassembly of section .text:
[0-9a-f]+ <foo>:
.*: 46041000 add.s \$f0,\$f2,\$f4
.*: 44420000 cfc1 \$2,\$0
#pass

3
gas/testsuite/gas/mips/mips1-fp.l Normal file

@ -0,0 +1,3 @@
.*: Assembler messages:
.*:6: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f0,\$f2,\$f4'
.*:7: Error: opcode not supported on this processor: .* \(.*\) `cfc1 \$2,\$0'

7
gas/testsuite/gas/mips/mips1-fp.s Normal file

@ -0,0 +1,7 @@
# Source file used to test -mips1 fp instructions.
# This is not a complete list of mips1 FP instructions.
foo:
add.s $f0,$f2,$f4
cfc1 $2,$0