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Add support for 64-bit ARM architecture: AArch64
This commit is contained in:
Nick Clifton
@ -1,3 +1,18 @@
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2012-08-13 Ian Bolton <ian.bolton@arm.com>
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Laurent Desnogues <laurent.desnogues@arm.com>
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Jim MacArthur <jim.macarthur@arm.com>
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Marcus Shawcroft <marcus.shawcroft@arm.com>
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Nigel Stephens <nigel.stephens@arm.com>
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Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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Richard Earnshaw <rearnsha@arm.com>
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Sofiane Naci <sofiane.naci@arm.com>
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Tejas Belagod <tejas.belagod@arm.com>
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Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64.h: New file.
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* common.h (EM_res183): Rename to EM_AARCH64.
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(EM_res184): Rename to EM_ARM184.
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2012-06-28 Iain Sandoe <iain@codesourcery.com>
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* common.h (AT_L1I_CACHESHAPE, AT_L1D_CACHESHAPE,
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214
include/elf/aarch64.h
Normal file
214
include/elf/aarch64.h
Normal file
@ -0,0 +1,214 @@
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/* AArch64 ELF support for BFD.
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Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GNU Binutils.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the license, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#ifndef _ELF_AARCH64_H
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#define _ELF_AARCH64_H
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#include "elf/reloc-macros.h"
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/* Processor specific program header types. */
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#define PT_AARCH64_ARCHEXT (PT_LOPROC + 0)
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/* Additional section types. */
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#define SHT_AARCH64_ATTRIBUTES 0x70000003 /* Section holds attributes. */
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/* AArch64-specific values for sh_flags. */
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#define SHF_ENTRYSECT 0x10000000 /* Section contains an
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entry point. */
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#define SHF_COMDEF 0x80000000 /* Section may be multiply defined
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in the input to a link step. */
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/* Relocation types. */
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START_RELOC_NUMBERS (elf_aarch64_reloc_type)
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/* Null relocations. */
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RELOC_NUMBER (R_AARCH64_NONE, 0) /* No reloc */
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FAKE_RELOC (R_AARCH64_static_min, 256)
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RELOC_NUMBER (R_AARCH64_NULL, 256) /* No reloc */
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/* Basic data relocations. */
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/* .xword: (S+A) */
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RELOC_NUMBER (R_AARCH64_ABS64, 257)
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/* .word: (S+A) */
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RELOC_NUMBER (R_AARCH64_ABS32, 258)
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/* .half: (S+A) */
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RELOC_NUMBER (R_AARCH64_ABS16, 259)
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/* .xword: (S+A-P) */
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RELOC_NUMBER (R_AARCH64_PREL64, 260)
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/* .word: (S+A-P) */
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RELOC_NUMBER (R_AARCH64_PREL32, 261)
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/* .half: (S+A-P) */
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RELOC_NUMBER (R_AARCH64_PREL16, 262)
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/* Group relocations to create a 16, 32, 48 or 64 bit
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unsigned data or abs address inline. */
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/* MOV[ZK]: ((S+A) >> 0) & 0xffff */
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RELOC_NUMBER (R_AARCH64_MOVW_UABS_G0, 263)
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/* MOV[ZK]: ((S+A) >> 0) & 0xffff */
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RELOC_NUMBER (R_AARCH64_MOVW_UABS_G0_NC, 264)
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/* MOV[ZK]: ((S+A) >> 16) & 0xffff */
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RELOC_NUMBER (R_AARCH64_MOVW_UABS_G1, 265)
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/* MOV[ZK]: ((S+A) >> 16) & 0xffff */
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RELOC_NUMBER (R_AARCH64_MOVW_UABS_G1_NC, 266)
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/* MOV[ZK]: ((S+A) >> 32) & 0xffff */
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RELOC_NUMBER (R_AARCH64_MOVW_UABS_G2, 267)
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/* MOV[ZK]: ((S+A) >> 32) & 0xffff */
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RELOC_NUMBER (R_AARCH64_MOVW_UABS_G2_NC, 268)
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/* MOV[ZK]: ((S+A) >> 48) & 0xffff */
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RELOC_NUMBER (R_AARCH64_MOVW_UABS_G3, 269)
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/* Group relocations to create high part of a 16, 32, 48 or 64 bit
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signed data or abs address inline. Will change instruction
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to MOVN or MOVZ depending on sign of calculated value. */
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/* MOV[ZN]: ((S+A) >> 0) & 0xffff */
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RELOC_NUMBER (R_AARCH64_MOVW_SABS_G0, 270)
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/* MOV[ZN]: ((S+A) >> 16) & 0xffff */
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RELOC_NUMBER (R_AARCH64_MOVW_SABS_G1, 271)
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/* MOV[ZN]: ((S+A) >> 32) & 0xffff */
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RELOC_NUMBER (R_AARCH64_MOVW_SABS_G2, 272)
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/* Relocations to generate 19, 21 and 33 bit PC-relative load/store
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addresses: PG(x) is (x & ~0xfff). */
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/* LD-lit: ((S+A-P) >> 2) & 0x7ffff */
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RELOC_NUMBER (R_AARCH64_LD_PREL_LO19, 273)
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/* ADR: (S+A-P) & 0x1fffff */
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RELOC_NUMBER (R_AARCH64_ADR_PREL_LO21, 274)
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/* ADRH: ((PG(S+A)-PG(P)) >> 12) & 0x1fffff */
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RELOC_NUMBER (R_AARCH64_ADR_PREL_PG_HI21, 275)
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/* ADRH: ((PG(S+A)-PG(P)) >> 12) & 0x1fffff */
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RELOC_NUMBER (R_AARCH64_ADR_PREL_PG_HI21_NC, 276)
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/* ADD: (S+A) & 0xfff */
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RELOC_NUMBER (R_AARCH64_ADD_ABS_LO12_NC, 277)
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/* LD/ST8: (S+A) & 0xfff */
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RELOC_NUMBER (R_AARCH64_LDST8_ABS_LO12_NC, 278)
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/* Relocations for control-flow instructions. */
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/* TBZ/NZ: ((S+A-P) >> 2) & 0x3fff. */
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RELOC_NUMBER (R_AARCH64_TSTBR14, 279)
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/* B.cond: ((S+A-P) >> 2) & 0x7ffff. */
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RELOC_NUMBER (R_AARCH64_CONDBR19, 280)
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/* 281 unused */
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/* B: ((S+A-P) >> 2) & 0x3ffffff. */
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RELOC_NUMBER (R_AARCH64_JUMP26, 282)
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/* BL: ((S+A-P) >> 2) & 0x3ffffff. */
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RELOC_NUMBER (R_AARCH64_CALL26, 283)
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/* LD/ST16: (S+A) & 0xffe */
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RELOC_NUMBER (R_AARCH64_LDST16_ABS_LO12_NC, 284)
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/* LD/ST32: (S+A) & 0xffc */
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RELOC_NUMBER (R_AARCH64_LDST32_ABS_LO12_NC, 285)
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/* LD/ST64: (S+A) & 0xff8 */
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RELOC_NUMBER (R_AARCH64_LDST64_ABS_LO12_NC, 286)
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/* LD/ST128: (S+A) & 0xff0 */
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RELOC_NUMBER (R_AARCH64_LDST128_ABS_LO12_NC, 299)
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RELOC_NUMBER (R_AARCH64_ADR_GOT_PAGE, 311)
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RELOC_NUMBER (R_AARCH64_LD64_GOT_LO12_NC, 312)
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FAKE_RELOC (R_AARCH64_static_max, 313)
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FAKE_RELOC (R_AARCH64_tls_min, 512)
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RELOC_NUMBER (R_AARCH64_TLSGD_ADR_PAGE21, 513)
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RELOC_NUMBER (R_AARCH64_TLSGD_ADD_LO12_NC, 514)
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RELOC_NUMBER (R_AARCH64_TLSIE_MOVW_GOTTPREL_G1, 539)
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RELOC_NUMBER (R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC, 540)
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RELOC_NUMBER (R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, 541)
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RELOC_NUMBER (R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, 542)
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RELOC_NUMBER (R_AARCH64_TLSIE_LD_GOTTPREL_PREL19, 543)
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RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G2, 544)
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RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G1, 545)
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RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G1_NC, 546)
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RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G0, 547)
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RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G0_NC, 548)
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RELOC_NUMBER (R_AARCH64_TLSLE_ADD_TPREL_HI12, 549)
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RELOC_NUMBER (R_AARCH64_TLSLE_ADD_TPREL_LO12, 550)
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RELOC_NUMBER (R_AARCH64_TLSLE_ADD_TPREL_LO12_NC, 551)
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FAKE_RELOC (R_AARCH64_tls_max, 552)
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FAKE_RELOC (R_AARCH64_tlsdesc_min, 560)
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RELOC_NUMBER (R_AARCH64_TLSDESC_LD64_PREL19, 560)
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RELOC_NUMBER (R_AARCH64_TLSDESC_ADR_PREL21, 561)
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RELOC_NUMBER (R_AARCH64_TLSDESC_ADR_PAGE, 562)
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RELOC_NUMBER (R_AARCH64_TLSDESC_LD64_LO12_NC, 563)
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RELOC_NUMBER (R_AARCH64_TLSDESC_ADD_LO12_NC, 564)
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RELOC_NUMBER (R_AARCH64_TLSDESC_OFF_G1, 565)
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RELOC_NUMBER (R_AARCH64_TLSDESC_OFF_G0_NC, 566)
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RELOC_NUMBER (R_AARCH64_TLSDESC_LDR, 567)
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RELOC_NUMBER (R_AARCH64_TLSDESC_ADD, 568)
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RELOC_NUMBER (R_AARCH64_TLSDESC_CALL, 569)
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FAKE_RELOC (R_AARCH64_tlsdesc_max, 570)
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/* Dynamic relocations */
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FAKE_RELOC (R_AARCH64_dyn_min, 1024)
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/* Copy symbol at runtime. */
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RELOC_NUMBER (R_AARCH64_COPY, 1024)
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/* Create GOT entry. */
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RELOC_NUMBER (R_AARCH64_GLOB_DAT, 1025)
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/* Create PLT entry. */
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RELOC_NUMBER (R_AARCH64_JUMP_SLOT, 1026)
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/* Adjust by program base. */
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RELOC_NUMBER (R_AARCH64_RELATIVE, 1027)
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RELOC_NUMBER (R_AARCH64_TLS_DTPMOD64, 1028)
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RELOC_NUMBER (R_AARCH64_TLS_DTPREL64, 1029)
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RELOC_NUMBER (R_AARCH64_TLS_TPREL64, 1030)
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RELOC_NUMBER (R_AARCH64_TLSDESC, 1031)
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FAKE_RELOC (R_AARCH64_dyn_max, 1032)
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END_RELOC_NUMBERS (R_AARCH64_end)
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#endif /* _ELF_AARCH64_H */
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@ -287,8 +287,8 @@
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#define EM_L1OM 180 /* Intel L1OM */
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#define EM_K1OM 181 /* Intel K1OM */
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#define EM_INTEL182 182 /* Reserved by Intel */
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#define EM_res183 183 /* Reserved by ARM */
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#define EM_res184 184 /* Reserved by ARM */
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#define EM_AARCH64 183 /* ARM 64-bit architecture */
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#define EM_ARM184 184 /* Reserved by ARM */
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#define EM_AVR32 185 /* Atmel Corporation 32-bit microprocessor family */
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#define EM_STM8 186 /* STMicroeletronics STM8 8-bit microcontroller */
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#define EM_TILE64 187 /* Tilera TILE64 multicore architecture family */
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