espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-09-10 05:52:21 +08:00
Code Issues Packages Projects Releases Wiki Activity

[AArch64][gas] Update MTE system register encodings

Browse Source 
The MTE specification adjusted the encoding of the TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12 system registers.
This patch brings binutils up to date.

The references for the encodings are at:
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsre0_el1 (also contains TFSR_EL12 description)
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el1
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el2
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el3

Tested check-gas for aarch64-none-elf.

opcodes/

	* aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
	tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
	(aarch64_sys_reg_supported_p): Update checks for the above.

gas/

    * testsuite/gas/aarch64/sysreg-4.d: Update expected disassembly for
    tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12 system registers.
This commit is contained in:
Kyrylo Tkachov
2019-08-22 10:20:01 +01:00
parent baf46cd780
commit a051e2f3e0
4 changed files with 31 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
(aarch64_sys_reg_supported_p): Update checks for the above.
2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for

20
opcodes/aarch64-opc.c
View File

@ -3966,11 +3966,11 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
{ "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
{ "tco", CPENC(3,3,C4,C2,7), F_ARCHEXT },
{ "tfsre0_el1", CPENC(3,0,C6,C6,1), F_ARCHEXT },
{ "tfsr_el1", CPENC(3,0,C6,C5,0), F_ARCHEXT },
{ "tfsr_el2", CPENC(3,4,C6,C5,0), F_ARCHEXT },
{ "tfsr_el3", CPENC(3,6,C6,C6,0), F_ARCHEXT },
{ "tfsr_el12", CPENC(3,5,C6,C6,0), F_ARCHEXT },
{ "tfsre0_el1", CPENC(3,0,C5,C6,1), F_ARCHEXT },
{ "tfsr_el1", CPENC(3,0,C5,C6,0), F_ARCHEXT },
{ "tfsr_el2", CPENC(3,4,C5,C6,0), F_ARCHEXT },
{ "tfsr_el3", CPENC(3,6,C5,C6,0), F_ARCHEXT },
{ "tfsr_el12", CPENC(3,5,C5,C6,0), F_ARCHEXT },
{ "rgsr_el1", CPENC(3,0,C1,C0,5), F_ARCHEXT },
{ "gcr_el1", CPENC(3,0,C1,C0,6), F_ARCHEXT },
{ "gmid_el1", CPENC(3,1,C0,C0,4), F_ARCHEXT | F_REG_READ }, /* RO */
@ -4439,11 +4439,11 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
/* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG. */
if ((reg->value == CPENC (3, 3, C4, C2, 7)
|| reg->value == CPENC (3, 0, C6, C6, 1)
|| reg->value == CPENC (3, 0, C6, C5, 0)
|| reg->value == CPENC (3, 4, C6, C5, 0)
|| reg->value == CPENC (3, 6, C6, C6, 0)
|| reg->value == CPENC (3, 5, C6, C6, 0)
|| reg->value == CPENC (3, 0, C5, C6, 1)
|| reg->value == CPENC (3, 0, C5, C6, 0)
|| reg->value == CPENC (3, 4, C5, C6, 0)
|| reg->value == CPENC (3, 6, C5, C6, 0)
|| reg->value == CPENC (3, 5, C5, C6, 0)
|| reg->value == CPENC (3, 0, C1, C0, 5)
|| reg->value == CPENC (3, 0, C1, C0, 6)
|| reg->value == CPENC (3, 1, C0, C0, 4))