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Disallow VEX/EVEX encoded instructions in 16-bit mode

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gas/

	PR gas/17421
	* config/tc-i386.c (md_assemble): Disallow VEX/EVEX encoded
	instructions in 16-bit mode.

gas/testsuite/

	PR gas/17421
	* gas/i386/i386.exp: Run inval-16.

	* gas/i386/inval-16.l: New file.
	* gas/i386/inval-16.s: Likewise.
This commit is contained in:
H.J. Lu
2014-09-23 11:12:23 -07:00
parent c4d9ceb647
commit 9e5e52835b
6 changed files with 57 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
gas/ChangeLog
View File

@ -1,3 +1,9 @@
2014-09-23 H.J. Lu <hongjiu.lu@intel.com>
PR gas/17421
* config/tc-i386.c (md_assemble): Disallow VEX/EVEX encoded
instructions in 16-bit mode.
2014-09-22 Alan Modra <amodra@gmail.com> 2014-09-22 Alan Modra <amodra@gmail.com>
* config/tc-m68k.c (md_assemble): Add assert to work around * config/tc-m68k.c (md_assemble): Add assert to work around

17
gas/config/tc-i386.c
View File

@ -3633,11 +3633,20 @@ md_assemble (char *line)
as_warn (_("translating to `%sp'"), i.tm.name); as_warn (_("translating to `%sp'"), i.tm.name);
} }
if (i.tm.opcode_modifier.vex) if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
build_vex_prefix (t); {
if (flag_code == CODE_16BIT)
{
as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
i.tm.name);
return;
}
if (i.tm.opcode_modifier.evex) if (i.tm.opcode_modifier.vex)
build_evex_prefix (); build_vex_prefix (t);
else
build_evex_prefix ();
}
/* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
instructions may define INT_OPCODE as well, so avoid this corner instructions may define INT_OPCODE as well, so avoid this corner

8
gas/testsuite/ChangeLog
View File

@ -1,3 +1,11 @@
2014-09-23 H.J. Lu <hongjiu.lu@intel.com>
PR gas/17421
* gas/i386/i386.exp: Run inval-16.
* gas/i386/inval-16.l: New file.
* gas/i386/inval-16.s: Likewise.
2014-09-22 H.J. Lu <hongjiu.lu@intel.com> 2014-09-22 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/cdr.d: New file. * gas/i386/cdr.d: New file.

1
gas/testsuite/gas/i386/i386.exp
View File

@ -42,6 +42,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_list_test "float" "-al -mmnemonic=att" run_list_test "float" "-al -mmnemonic=att"
run_list_test "general" "-al --listing-lhs-width=2 -mold-gcc" run_list_test "general" "-al --listing-lhs-width=2 -mold-gcc"
run_list_test "inval" "-al" run_list_test "inval" "-al"
run_list_test "inval-16" "-al"
run_list_test "segment" "-al" run_list_test "segment" "-al"
run_list_test "inval-seg" "-al" run_list_test "inval-seg" "-al"
run_list_test "inval-reg" "-al" run_list_test "inval-reg" "-al"

20
gas/testsuite/gas/i386/inval-16.l Normal file
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@ -0,0 +1,20 @@
.*: Assembler messages:
.*:3: Error: .*
.*:4: Error: .*
.*:5: Error: .*
.*:6: Error: .*
.*:7: Error: .*
.*:8: Error: .*
.*:9: Error: .*
GAS LISTING .*
[ ]*1[ ]+\.text
[ ]*2[ ]+\.code16
[ ]*3[ ]+vmovapd %xmm0,%xmm1
[ ]*4[ ]+vaddsd %xmm4, %xmm5, %xmm6\{%k7\}
[ ]*5[ ]+vfrczpd %xmm7,%xmm7
[ ]*6[ ]+andn \(%eax\), %ecx, %ecx
[ ]*7[ ]+bzhi %ecx, \(%eax\), %ecx
[ ]*8[ ]+llwpcb %ecx
[ ]*9[ ]+blcfill %ecx, %ecx

9
gas/testsuite/gas/i386/inval-16.s Normal file
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@ -0,0 +1,9 @@
.text
.code16
vmovapd %xmm0,%xmm1
vaddsd %xmm4, %xmm5, %xmm6{%k7}
vfrczpd %xmm7,%xmm7
andn (%eax), %ecx, %ecx
bzhi %ecx, (%eax), %ecx
llwpcb %ecx
blcfill %ecx, %ecx