Power10 VSX load/store rightmost element operations

opcodes/
	* ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
	stxvrbx, stxvrhx, stxvrwx, stxvrdx.
gas/
	* testsuite/gas/ppc/rightmost.d,
	* testsuite/gas/ppc/rightmost.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.

gas/ChangeLog

@@ -1,3 +1,9 @@
+2020-05-11  Alan Modra  <amodra@gmail.com>
+
+	* testsuite/gas/ppc/rightmost.d,
+	* testsuite/gas/ppc/rightmost.s: New test.
+	* testsuite/gas/ppc/ppc.exp: Run it.
+
 2020-05-11  Alan Modra  <amodra@gmail.com>
 
 	* testsuite/gas/ppc/xvtlsbb.d,

gas/testsuite/gas/ppc/ppc.exp

@@ -144,3 +144,4 @@ run_dump_test "bitmanip"
 run_dump_test "set_bool"
 run_dump_test "stringop"
 run_dump_test "xvtlsbb"
+run_dump_test "rightmost"

gas/testsuite/gas/ppc/rightmost.d

@@ -0,0 +1,17 @@
+#as: -mpower10
+#objdump: -dr -Mpower10
+
+.*
+
+
+Disassembly of section \.text:
+
+0+0 <_start>:
+.*:	(7f ef 80 1b|1b 80 ef 7f) 	lxvrbx  vs63,r15,r16
+.*:	(7f d1 90 5b|5b 90 d1 7f) 	lxvrhx  vs62,r17,r18
+.*:	(7f b3 a0 9b|9b a0 b3 7f) 	lxvrwx  vs61,r19,r20
+.*:	(7f 95 b0 db|db b0 95 7f) 	lxvrdx  vs60,r21,r22
+.*:	(7c 17 c1 1a|1a c1 17 7c) 	stxvrbx vs0,r23,r24
+.*:	(7c 39 d1 5a|5a d1 39 7c) 	stxvrhx vs1,r25,r26
+.*:	(7c 5b e1 9a|9a e1 5b 7c) 	stxvrwx vs2,r27,r28
+.*:	(7c 7d f1 da|da f1 7d 7c) 	stxvrdx vs3,r29,r30

gas/testsuite/gas/ppc/rightmost.s

@@ -0,0 +1,10 @@
+	.text
+_start:
+	lxvrbx	63,15,16
+	lxvrhx	62,17,18
+	lxvrwx	61,19,20
+	lxvrdx	60,21,22
+	stxvrbx	0,23,24
+	stxvrhx	1,25,26
+	stxvrwx	2,27,28
+	stxvrdx	3,29,30

opcodes/ChangeLog

@@ -1,3 +1,8 @@
+2020-05-11  Alan Modra  <amodra@gmail.com>
+
+	* ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
+	stxvrbx, stxvrhx, stxvrwx, stxvrdx.
+
 2020-05-11  Alan Modra  <amodra@gmail.com>
 
 	* ppc-opc.c (powerpc_opcodes): Add xvtlsbb.

opcodes/ppc-opc.c

@@ -6033,6 +6033,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lxsiwzx",	X(31,12),	XX1_MASK,    PPCVSX2,	0,		{XT6, RA0, RB}},
 
+{"lxvrbx",	X(31,13),	XX1_MASK,    POWER10,	0,		{XT6, RA0, RB}},
+
 {"isellt",	X(31,15),	X_MASK,	     PPCISEL,	0,		{RT, RA0, RB}},
 
 {"tlbilxlpid",	XTO(31,18,0),	XTO_MASK, E500MC|PPCA2,	0,		{0}},
@@ -6087,6 +6089,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"lvehx",	X(31,39),	X_MASK,	     PPCVEC,	0,		{VD, RA0, RB}},
 {"lhfcmx",	APU(31,39,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
 
+{"lxvrhx",	X(31,45),	XX1_MASK,    POWER10,	0,		{XT6, RA0, RB}},
+
 {"mviwsplt",	X(31,46),	X_MASK,	     E6500,	0,		{VD, RA, RB}},
 
 {"iselgt",	X(31,47),	X_MASK,	     PPCISEL,	0,		{RT, RA0, RB}},
@@ -6097,6 +6101,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lxsiwax",	X(31,76),	XX1_MASK,    PPCVSX2,	0,		{XT6, RA0, RB}},
 
+{"lxvrwx",	X(31,77),	XX1_MASK,    POWER10,	0,		{XT6, RA0, RB}},
+
 {"iseleq",	X(31,79),	X_MASK,	     PPCISEL,	0,		{RT, RA0, RB}},
 
 {"isel",	XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0,		{RT, RA0, RB, CRB}},
@@ -6185,6 +6191,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mul",		XO(31,107,0,0),	XO_MASK,     M601,	0,		{RT, RA, RB}},
 {"mul.",	XO(31,107,0,1),	XO_MASK,     M601,	0,		{RT, RA, RB}},
 
+{"lxvrdx",	X(31,109),	XX1_MASK,    POWER10,	0,		{XT6, RA0, RB}},
+
 {"mvidsplt",	X(31,110),	X_MASK,	     E6500,	0,		{VD, RA, RB}},
 
 {"mtsrdin",	X(31,114),	XRA_MASK,    PPC64,	0,		{RS, RB}},
@@ -6229,6 +6237,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"stxsiwx",	X(31,140),	XX1_MASK,    PPCVSX2,	0,		{XS6, RA0, RB}},
 
+{"stxvrbx",	X(31,141),	XX1_MASK,    POWER10,	0,		{XT6, RA0, RB}},
+
 {"msgsndp",	XRTRA(31,142,0,0), XRTRA_MASK, POWER8,	0,		{RB}},
 {"dcbtstlse",	X(31,142),	X_MASK,	     PPCCHLK,	E500MC,		{CT, RA0, RB}},
 
@@ -6274,6 +6284,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"addex",	ZRC(31,170,0),	Z2_MASK,     POWER9,	0,		{RT, RA, RB, CY}},
 
+{"stxvrhx",	X(31,173),	XX1_MASK,    POWER10,	0,		{XT6, RA0, RB}},
+
 {"msgclrp",	XRTRA(31,174,0,0), XRTRA_MASK, POWER8,	0,		{RB}},
 {"dcbtlse",	X(31,174),	X_MASK,	     PPCCHLK,	E500MC,		{CT, RA0, RB}},
 
@@ -6321,6 +6333,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"addze.",	XO(31,202,0,1),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
 {"aze.",	XO(31,202,0,1),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
 
+{"stxvrwx",	X(31,205),	XX1_MASK,    POWER10,	0,		{XT6, RA0, RB}},
+
 {"msgsnd",	XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0,	{RB}},
 
 {"mtsr",	X(31,210), XRB_MASK|(1<<20), COM,	NON32,		{SR, RS}},
@@ -6372,6 +6386,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mullw.",	XO(31,235,0,1),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
 {"muls.",	XO(31,235,0,1),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
 
+{"stxvrdx",	X(31,237),	XX1_MASK,    POWER10,	0,		{XT6, RA0, RB}},
+
 {"icblce",	X(31,238),	X_MASK,	     PPCCHLK,	E500MC|PPCA2,	{CT, RA, RB}},
 {"msgclr",	XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0,	{RB}},
 {"mtsrin",	X(31,242),	XRA_MASK,    PPC,	NON32,		{RS, RB}},