Apply patch supplied for case 102229 to implement new insns psrclr and psrset.

gas/config/tc-mcore.c

@@ -45,11 +45,12 @@ static int    log2 PARAMS ((unsigned int));
 static char * parse_reg    PARAMS ((char *, unsigned *));
 static char * parse_creg   PARAMS ((char *, unsigned *));
 static char * parse_exp    PARAMS ((char *, expressionS *));
-static void   make_name PARAMS ((char *, char *, int));
-static int    enter_literal PARAMS ((expressionS *, int));
 static char * parse_rt     PARAMS ((char *, char **, int, expressionS *));
 static char * parse_imm    PARAMS ((char *, unsigned *, unsigned, unsigned));
 static char * parse_mem    PARAMS ((char *, unsigned *, unsigned *, unsigned));
+static char * parse_psrmod PARAMS ((char *, unsigned *));
+static void   make_name PARAMS ((char *, char *, int));
+static int    enter_literal PARAMS ((expressionS *, int));
 static void   dump_literals PARAMS ((int));
 static void   check_literals PARAMS ((int, int));
 static void   mcore_s_text    PARAMS ((int));
@@ -60,7 +61,6 @@ static void   mcore_s_bss     PARAMS ((int));
 static void   mcore_s_comm    PARAMS ((int));
 #endif
 
-
 /* Several places in this file insert raw instructions into the
    object. They should use MCORE_INST_XXX macros to get the opcodes
    and then use these two macros to crack the MCORE_INST value into
@@ -336,16 +336,17 @@ mcore_fill (unused)
 	}
 
       poolspan += size * repeat;
+      
+      check_literals (1, 0);
     }
   
   s_fill (unused);
 
-  check_literals (2, 0);
+  check_literals (1, 0);
 }
 
 /* Handle the section changing pseudo-ops.  These call through to the
    normal implementations, but they dump the literal pool first.  */
-
 static void
 mcore_s_text (ignore)
      int ignore;
@@ -588,6 +589,46 @@ parse_creg (s, reg)
   return s;
 }
 
+static char *
+parse_psrmod (s, reg)
+  char *     s;
+  unsigned * reg;
+{
+  int  i;
+  char buf[10];
+  static struct psrmods
+  {
+    char *       name;
+    unsigned int value;
+  }
+  psrmods[] =
+  {
+    { "ie", 1 },
+    { "fe", 2 },
+    { "ee", 4 },
+    { "af", 8 }	/* really 0 and non-combinable */
+  };
+  
+  for (i = 0; i < 2; i++)
+    buf[i] = isascii (s[i]) ? tolower (s[i]) : 0;
+  
+  for (i = sizeof (psrmods) / sizeof (psrmods[0]); i--;)
+    {
+      if (! strncmp (psrmods[i].name, buf, 2))
+	{
+          * reg = psrmods[i].value;
+	  
+          return s + 2;
+	}
+    }
+  
+  as_bad (_("bad/missing psr specifier"));
+  
+  * reg = 0;
+  
+  return s;
+}
+
 static char *
 parse_exp (s, e)
      char * s;
@@ -713,7 +754,7 @@ check_literals (kind, offset)
   
   if (poolspan > SPANCLOSE && kind > 0)
     dump_literals (0);
-  else if (poolspan > SPANEXIT && kind > 1)
+  else if (/* poolspan > SPANEXIT &&*/ kind > 1)
     dump_literals (0);
   else if (poolspan >= (SPANPANIC - poolsize * 2))
     dump_literals (1);
@@ -1594,6 +1635,29 @@ md_assemble (str)
       output = frag_more (2);
       break;
 
+    case OPSR:
+      op_end = parse_psrmod (op_end + 1, & reg);
+      
+      /* Look for further selectors.  */
+      while (* op_end == ',')
+	{
+	  unsigned value;
+	    
+	  op_end = parse_psrmod (op_end + 1, & value);
+	  
+	  if (value & reg)
+	    as_bad (_("duplicated psr bit specifier"));
+	  
+	  reg |= value;
+	}
+      
+      if (reg > 8)
+	as_bad (_("`af' must appear alone"));
+	
+      inst |= (reg & 0x7);
+      output = frag_more (2);
+      break;
+ 
     default:
       as_bad (_("unimplemented opcode \"%s\""), name);
     }

opcodes/ChangeLog

@@ -1,3 +1,11 @@
+1999-10-25  Nick Clifton  <nickc@cygnus.com>
+
+	* mcore-opc.h (enum mcore_opclass): Add class OPSR.
+	(mcore_table): Add psrclr and psrset instructions.
+
+	* mcore-dis.c (array imsk): Add mask for OPSR class.
+	(print_insn_mcore): Add decode for OPSR class insns.
+
 1999-10-18  Michael Meissner  <meissner@cygnus.com>
 
 	* alpha-opc.c (alpha_operands): Fill in missing initializer.

opcodes/mcore-dis.c

@@ -57,6 +57,52 @@ static const unsigned short imsk[] =
     /* OMc */ 0xFF00,
     /* SIa */ 0xFE00,
 
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include <stdio.h>
+#define STATIC_TABLE
+#define DEFINE_TABLE
+
+#include "mcore-opc.h"
+#include "dis-asm.h"
+
+/* Mask for each mcore_opclass: */
+static const unsigned short imsk[] =
+{
+    /* O0  */ 0xFFFF,
+    /* OT  */ 0xFFFC,
+    /* O1  */ 0xFFF0,
+    /* OC  */ 0xFFE0,
+    /* O2  */ 0xFF00,
+    /* X1  */ 0xFFF0,
+    /* OI  */ 0xFE00,
+    /* OB  */ 0xFE00,
+	      
+    /* OMa */ 0xFFF0,
+    /* SI  */ 0xFE00,
+    /* I7  */ 0xF800,
+    /* LS  */ 0xF000,
+    /* BR  */ 0xF800,
+    /* BL  */ 0xFF00,
+    /* LR  */ 0xF000,
+    /* LJ  */ 0xFF00,
+	      
+    /* RM  */ 0xFFF0,
+    /* RQ  */ 0xFFF0,
+    /* JSR */ 0xFFF0,
+    /* JMP */ 0xFFF0,
+    /* OBRa*/ 0xFFF0,
+    /* OBRb*/ 0xFF80,
+    /* OBRc*/ 0xFF00,
+    /* OBR2*/ 0xFE00,
+	      
+    /* O1R1*/ 0xFFF0,
+    /* OMb */ 0xFF80,
+    /* OMc */ 0xFF00,
+    /* SIa */ 0xFE00,
+
+  /* OPSR  */ 0xFFF8,   /* psrset/psrclr */
+		 
     /* JC  */ 0,		/* JC,JU,JL don't appear in object */
     /* JU  */ 0,
     /* JL  */ 0,
@@ -237,6 +283,18 @@ print_insn_mcore (memaddr, info)
 	  }
 	  break;
 	  
+	case OPSR:
+	  {
+	    static char * fields[] = 
+	    {
+	      "af", "ie",    "fe",    "fe,ie", 
+	      "ee", "ee,ie", "ee,fe", "ee,fe,ie"
+	    };
+	    
+	    fprintf (stream, "\t%s", fields[inst & 0x7]);
+	  }
+	  break;
+
 	default:
 	  /* if the disassembler lags the instruction set */
 	  fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);

opcodes/mcore-opc.h

@@ -23,7 +23,7 @@ typedef enum
   O0,    OT,   O1,   OC,   O2,    X1,    OI,    OB,
   OMa,   SI,   I7,   LS,   BR,    BL,    LR,    LJ,
   RM,    RQ,   JSR,  JMP,  OBRa,  OBRb,  OBRc,  OBR2,
-  O1R1,  OMb,  OMc,  SIa,
+  O1R1,  OMb,  OMc,  SIa,  OPSR,
   JC,    JU,   JL,   RSI,  DO21,  OB2
 }
 mcore_opclass;
@@ -99,6 +99,8 @@ mcore_opcode_info mcore_table[] =
   { "tst",	O2,	0,	0x0E00 },
   { "cmpne",	O2,	0,	0x0F00 },
   { "mfcr",	OC,	0,	0x1000 },
+  { "psrclr",	OPSR,	0,	0x11F0 },
+  { "psrset",	OPSR,	0,	0x11F8 },
   { "mov",	O2,	0,	0x1200 },
   { "bgenr",	O2,	0,	0x1300 },
   { "rsub",	O2,	0,	0x1400 },