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x86: drop redundant VSIB handling code

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The vecsib && !base_reg case is already being handled (in a more correct
manner) by earlier code.
This commit is contained in:
Jan Beulich
2017-11-23 11:00:44 +01:00
committed by Jan Beulich
parent 66f1eba0b7
commit 9bb129e82f
2 changed files with 6 additions and 7 deletions
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5
gas/ChangeLog
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@ -1,3 +1,8 @@
2017-11-23 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (build_modrm_byte): Drop VSIB handling from
code also setting fake_zero_displacement.
2017-11-23 Jan Beulich <jbeulich@suse.com> 2017-11-23 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/arch-4.s: Correct ud1 and ud2b. Add ud0. * testsuite/gas/i386/arch-4.s: Correct ud1 and ud2b. Add ud0.

8
gas/config/tc-i386.c
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@ -6591,13 +6591,7 @@ build_modrm_byte (void)
{ {
i.rm.mode = 0; i.rm.mode = 0;
if (!i.disp_operands) if (!i.disp_operands)
{ fake_zero_displacement = 1;
fake_zero_displacement = 1;
/* Instructions with VSIB byte need 32bit displacement
if there is no base register. */
if (i.tm.opcode_modifier.vecsib)
i.types[op].bitfield.disp32 = 1;
}
if (i.index_reg == 0) if (i.index_reg == 0)
{ {
gas_assert (!i.tm.opcode_modifier.vecsib); gas_assert (!i.tm.opcode_modifier.vecsib);