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or1k: add support for l.swa/l.lwa atomic instructions
This adds support for the load-link/store-conditional l.lwa/l.swa atomic instructions. The support is added in such way, that the cpu description not only describes the mnemonics, but also the functionality. A couple of fixes to typos in nearby/related code are also snuck into this. cpu/ * or1korbis.cpu (h-atomic-reserve): New hardware. (h-atomic-address): Likewise. (insn-opcode): Add opcodes for LWA and SWA. (atomic-reserve): New operand. (atomic-address): Likewise. (l-lwa, l-swa): New instructions. (l-lbs): Fix typo in comment. (store-insn): Clear atomic reserve on store to atomic-address. Fix register names in fmt field. opcodes/ * or1k-desc.c: Regenerated. * or1k-desc.h: Likewise. * or1k-opc.c: Likewise. * or1k-opc.h: Likewise. * or1k-opinst.c: Likewise.
This commit is contained in:
Stefan Kristiansson
@ -1,3 +1,15 @@
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2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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* or1korbis.cpu (h-atomic-reserve): New hardware.
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(h-atomic-address): Likewise.
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(insn-opcode): Add opcodes for LWA and SWA.
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(atomic-reserve): New operand.
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(atomic-address): Likewise.
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(l-lwa, l-swa): New instructions.
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(l-lbs): Fix typo in comment.
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(store-insn): Clear atomic reserve on store to atomic-address.
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Fix register names in fmt field.
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2014-04-22 Christian Svensson <blue@cmd.nu>
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* openrisc.cpu: Delete.
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@ -24,6 +24,10 @@
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(dnh h-uimm16 "16-bit unsigned immediate" () (immediate (UINT 16)) () () ())
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(dnh h-uimm6 "6-bit unsigned immediate" () (immediate (UINT 6)) () () ())
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; Hardware for the (internal) atomic registers
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(dsh h-atomic-reserve "atomic reserve flag" () (register BI))
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(dsh h-atomic-address "atomic reserve address" () (register SI))
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; Instruction classes.
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(dnf f-opcode "insn opcode" ((MACH ORBIS-MACHS)) 31 6)
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@ -139,6 +143,7 @@
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("JR" #x11)
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("JALR" #x12)
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("MACI" #x13)
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("LWA" #x1b)
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("CUST1" #x1c)
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("CUST2" #x1d)
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("CUST3" #x1e)
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@ -162,6 +167,7 @@
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("MTSPR" #x30)
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("MAC" #x31)
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("FLOAT" #x32)
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("SWA" #x33)
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("SD" #x34)
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("SW" #x35)
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("SB" #x36)
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@ -286,6 +292,9 @@
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(dnop mac-machi "MAC HI result register" ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-machi f-nil)
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(dnop mac-maclo "MAC LO result register" ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-maclo f-nil)
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(dnop atomic-reserve "atomic reserve flag" ((MACH ORBIS-MACHS) SEM-ONLY) h-atomic-reserve f-nil)
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(dnop atomic-address "atomic address" ((MACH ORBIS-MACHS) SEM-ONLY) h-atomic-address f-nil)
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(dnop uimm6 "uimm6" ((MACH ORBIS-MACHS)) h-uimm6 f-uimm6)
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(dnop rD "destination register" ((MACH ORBIS-MACHS)) h-gpr f-r1)
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@ -572,6 +581,18 @@
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()
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)
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(dni l-lwa "l.lwa reg/simm16(reg)"
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((MACH ORBIS-MACHS))
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"l.lwa $rD,${simm16}($rA)"
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(+ OPC_LWA rD rA simm16)
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(sequence ()
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(set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4))))
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(set atomic-reserve (const 1))
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(set atomic-address (load-store-addr rA simm16 4))
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)
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()
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)
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(dni l-lbz "l.lbz reg/simm16(reg)"
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((MACH ORBIS-MACHS))
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"l.lbz $rD,${simm16}($rA)"
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@ -580,7 +601,7 @@
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()
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)
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(dni l-lbs "l.lbz reg/simm16(reg)"
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(dni l-lbs "l.lbs reg/simm16(reg)"
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((MACH ORBIS-MACHS))
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"l.lbs $rD,${simm16}($rA)"
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(+ OPC_LBS rD rA simm16)
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@ -613,8 +634,14 @@
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(.str "l." mnemonic " simm16(reg)/reg")
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((MACH ORBIS-MACHS))
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(.str "l." mnemonic " ${simm16-split}($rA),$rB")
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(+ opc-op rB rD simm16-split)
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(set mode (mem mode (load-store-addr rA simm16-split size)) (trunc mode rB))
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(+ opc-op rA rB simm16-split)
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(sequence ((SI addr))
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(set addr (load-store-addr rA simm16-split size))
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(set mode (mem mode addr) (trunc mode rB))
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(if (eq (and addr #xffffffc) atomic-address)
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(set atomic-reserve (const 0))
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)
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)
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()
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)
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)
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@ -624,6 +651,20 @@
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(store-insn sb OPC_SB UQI 1)
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(store-insn sh OPC_SH UHI 2)
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(dni l-swa "l.swa simm16(reg)/reg"
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((MACH ORBIS-MACHS))
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"l.swa ${simm16-split}($rA),$rB"
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(+ OPC_SWA rA rB simm16)
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(sequence ((SI addr) (BI flag))
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(set addr (load-store-addr rA simm16-split 4))
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(set sys-sr-f (and atomic-reserve (eq addr atomic-address)))
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(if sys-sr-f
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(set USI (mem USI addr) (trunc USI rB))
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)
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(set atomic-reserve (const 0))
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)
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()
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)
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; Shift and rotate instructions
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@ -1,3 +1,11 @@
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2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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* or1k-desc.c: Regenerated.
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* or1k-desc.h: Likewise.
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* or1k-opc.c: Likewise.
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* or1k-opc.h: Likewise.
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* or1k-opinst.c: Likewise.
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2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
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* mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
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@ -919,6 +919,8 @@ const CGEN_HW_ENTRY or1k_cgen_hw_table[] =
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{ "h-simm16", HW_H_SIMM16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
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{ "h-uimm16", HW_H_UIMM16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ "h-uimm6", HW_H_UIMM6, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ "h-atomic-reserve", HW_H_ATOMIC_RESERVE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ "h-atomic-address", HW_H_ATOMIC_ADDRESS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
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};
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@ -1059,6 +1061,14 @@ const CGEN_OPERAND or1k_cgen_operand_table[] =
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{ "mac-maclo", OR1K_OPERAND_MAC_MACLO, HW_H_MAC_MACLO, 0, 0,
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{ 0, { (const PTR) 0 } },
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{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
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/* atomic-reserve: atomic reserve flag */
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{ "atomic-reserve", OR1K_OPERAND_ATOMIC_RESERVE, HW_H_ATOMIC_RESERVE, 0, 0,
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{ 0, { (const PTR) 0 } },
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{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
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/* atomic-address: atomic address */
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{ "atomic-address", OR1K_OPERAND_ATOMIC_ADDRESS, HW_H_ATOMIC_ADDRESS, 0, 0,
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{ 0, { (const PTR) 0 } },
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{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
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/* uimm6: uimm6 */
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{ "uimm6", OR1K_OPERAND_UIMM6, HW_H_UIMM6, 5, 6,
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{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM6] } },
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@ -1224,6 +1234,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
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OR1K_INSN_L_LWS, "l-lws", "l.lws", 32,
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{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
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},
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/* l.lwa $rD,${simm16}($rA) */
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{
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OR1K_INSN_L_LWA, "l-lwa", "l.lwa", 32,
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{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
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},
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/* l.lbz $rD,${simm16}($rA) */
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{
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OR1K_INSN_L_LBZ, "l-lbz", "l.lbz", 32,
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@ -1259,6 +1274,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
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OR1K_INSN_L_SH, "l-sh", "l.sh", 32,
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{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
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},
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/* l.swa ${simm16-split}($rA),$rB */
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{
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OR1K_INSN_L_SWA, "l-swa", "l.swa", 32,
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{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
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},
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/* l.sll $rD,$rA,$rB */
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{
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OR1K_INSN_L_SLL, "l-sll", "l.sll", 32,
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@ -277,15 +277,15 @@ typedef enum insn_opcode {
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OPC_J = 0, OPC_JAL = 1, OPC_BNF = 3, OPC_BF = 4
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, OPC_NOP = 5, OPC_MOVHIMACRC = 6, OPC_SYSTRAPSYNCS = 8, OPC_RFE = 9
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, OPC_VECTOR = 10, OPC_JR = 17, OPC_JALR = 18, OPC_MACI = 19
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, OPC_CUST1 = 28, OPC_CUST2 = 29, OPC_CUST3 = 30, OPC_CUST4 = 31
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, OPC_LD = 32, OPC_LWZ = 33, OPC_LWS = 34, OPC_LBZ = 35
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, OPC_LBS = 36, OPC_LHZ = 37, OPC_LHS = 38, OPC_ADDI = 39
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, OPC_ADDIC = 40, OPC_ANDI = 41, OPC_ORI = 42, OPC_XORI = 43
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, OPC_MULI = 44, OPC_MFSPR = 45, OPC_SHROTI = 46, OPC_SFI = 47
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, OPC_MTSPR = 48, OPC_MAC = 49, OPC_FLOAT = 50, OPC_SD = 52
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, OPC_SW = 53, OPC_SB = 54, OPC_SH = 55, OPC_ALU = 56
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, OPC_SF = 57, OPC_CUST5 = 60, OPC_CUST6 = 61, OPC_CUST7 = 62
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, OPC_CUST8 = 63
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, OPC_LWA = 27, OPC_CUST1 = 28, OPC_CUST2 = 29, OPC_CUST3 = 30
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, OPC_CUST4 = 31, OPC_LD = 32, OPC_LWZ = 33, OPC_LWS = 34
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, OPC_LBZ = 35, OPC_LBS = 36, OPC_LHZ = 37, OPC_LHS = 38
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, OPC_ADDI = 39, OPC_ADDIC = 40, OPC_ANDI = 41, OPC_ORI = 42
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, OPC_XORI = 43, OPC_MULI = 44, OPC_MFSPR = 45, OPC_SHROTI = 46
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, OPC_SFI = 47, OPC_MTSPR = 48, OPC_MAC = 49, OPC_FLOAT = 50
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, OPC_SWA = 51, OPC_SD = 52, OPC_SW = 53, OPC_SB = 54
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, OPC_SH = 55, OPC_ALU = 56, OPC_SF = 57, OPC_CUST5 = 60
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, OPC_CUST6 = 61, OPC_CUST7 = 62, OPC_CUST8 = 63
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} INSN_OPCODE;
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/* Enum declaration for systrapsync insn opcode enums. */
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@ -582,7 +582,7 @@ typedef enum cgen_hw_type {
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, HW_H_SYS_FPCSR_RM, HW_H_SYS_FPCSR_OVF, HW_H_SYS_FPCSR_UNF, HW_H_SYS_FPCSR_SNF
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, HW_H_SYS_FPCSR_QNF, HW_H_SYS_FPCSR_ZF, HW_H_SYS_FPCSR_IXF, HW_H_SYS_FPCSR_IVF
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, HW_H_SYS_FPCSR_INF, HW_H_SYS_FPCSR_DZF, HW_H_SIMM16, HW_H_UIMM16
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, HW_H_UIMM6, HW_MAX
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, HW_H_UIMM6, HW_H_ATOMIC_RESERVE, HW_H_ATOMIC_ADDRESS, HW_MAX
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} CGEN_HW_TYPE;
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#define MAX_HW ((int) HW_MAX)
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@ -615,15 +615,15 @@ typedef enum cgen_operand_type {
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OR1K_OPERAND_PC, OR1K_OPERAND_SYS_SR, OR1K_OPERAND_SYS_ESR0, OR1K_OPERAND_SYS_EPCR0
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, OR1K_OPERAND_SYS_SR_LEE, OR1K_OPERAND_SYS_SR_F, OR1K_OPERAND_SYS_SR_CY, OR1K_OPERAND_SYS_SR_OV
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, OR1K_OPERAND_SYS_SR_OVE, OR1K_OPERAND_SYS_CPUCFGR_OB64S, OR1K_OPERAND_SYS_CPUCFGR_ND, OR1K_OPERAND_SYS_FPCSR_RM
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, OR1K_OPERAND_MAC_MACHI, OR1K_OPERAND_MAC_MACLO, OR1K_OPERAND_UIMM6, OR1K_OPERAND_RD
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, OR1K_OPERAND_RA, OR1K_OPERAND_RB, OR1K_OPERAND_DISP26, OR1K_OPERAND_SIMM16
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, OR1K_OPERAND_UIMM16, OR1K_OPERAND_SIMM16_SPLIT, OR1K_OPERAND_UIMM16_SPLIT, OR1K_OPERAND_RDSF
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, OR1K_OPERAND_RASF, OR1K_OPERAND_RBSF, OR1K_OPERAND_RDDF, OR1K_OPERAND_RADF
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, OR1K_OPERAND_RBDF, OR1K_OPERAND_MAX
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, OR1K_OPERAND_MAC_MACHI, OR1K_OPERAND_MAC_MACLO, OR1K_OPERAND_ATOMIC_RESERVE, OR1K_OPERAND_ATOMIC_ADDRESS
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, OR1K_OPERAND_UIMM6, OR1K_OPERAND_RD, OR1K_OPERAND_RA, OR1K_OPERAND_RB
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, OR1K_OPERAND_DISP26, OR1K_OPERAND_SIMM16, OR1K_OPERAND_UIMM16, OR1K_OPERAND_SIMM16_SPLIT
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, OR1K_OPERAND_UIMM16_SPLIT, OR1K_OPERAND_RDSF, OR1K_OPERAND_RASF, OR1K_OPERAND_RBSF
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, OR1K_OPERAND_RDDF, OR1K_OPERAND_RADF, OR1K_OPERAND_RBDF, OR1K_OPERAND_MAX
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} CGEN_OPERAND_TYPE;
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/* Number of operands types. */
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#define MAX_OPERANDS 29
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#define MAX_OPERANDS 31
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/* Maximum number of operands referenced by any insn. */
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#define MAX_OPERAND_INSTANCES 9
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@ -88,7 +88,11 @@ static const CGEN_IFMT ifmt_l_lwz ATTRIBUTE_UNUSED = {
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};
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static const CGEN_IFMT ifmt_l_sw ATTRIBUTE_UNUSED = {
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32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R3) }, { F (F_SIMM16_SPLIT) }, { 0 } }
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32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R2) }, { F (F_R3) }, { F (F_SIMM16_SPLIT) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_l_swa ATTRIBUTE_UNUSED = {
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32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R2) }, { F (F_R3) }, { F (F_SIMM16) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_l_sll ATTRIBUTE_UNUSED = {
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@ -276,6 +280,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
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{ { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
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& ifmt_l_lwz, { 0x88000000 }
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},
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/* l.lwa $rD,${simm16}($rA) */
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{
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{ 0, 0, 0, 0 },
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{ { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
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& ifmt_l_lwz, { 0x6c000000 }
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},
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/* l.lbz $rD,${simm16}($rA) */
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{
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{ 0, 0, 0, 0 },
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@ -318,6 +328,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
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{ { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } },
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& ifmt_l_sw, { 0xdc000000 }
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},
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/* l.swa ${simm16-split}($rA),$rB */
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{
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{ 0, 0, 0, 0 },
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{ { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } },
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& ifmt_l_swa, { 0xcc000000 }
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},
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/* l.sll $rD,$rA,$rB */
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{
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{ 0, 0, 0, 0 },
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@ -39,32 +39,33 @@ typedef enum cgen_insn_type {
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, OR1K_INSN_L_JALR, OR1K_INSN_L_BNF, OR1K_INSN_L_BF, OR1K_INSN_L_TRAP
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, OR1K_INSN_L_SYS, OR1K_INSN_L_RFE, OR1K_INSN_L_NOP_IMM, OR1K_INSN_L_NOP
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, OR1K_INSN_L_MOVHI, OR1K_INSN_L_MACRC, OR1K_INSN_L_MFSPR, OR1K_INSN_L_MTSPR
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, OR1K_INSN_L_LWZ, OR1K_INSN_L_LWS, OR1K_INSN_L_LBZ, OR1K_INSN_L_LBS
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, OR1K_INSN_L_LHZ, OR1K_INSN_L_LHS, OR1K_INSN_L_SW, OR1K_INSN_L_SB
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, OR1K_INSN_L_SH, OR1K_INSN_L_SLL, OR1K_INSN_L_SLLI, OR1K_INSN_L_SRL
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||||
, OR1K_INSN_L_SRLI, OR1K_INSN_L_SRA, OR1K_INSN_L_SRAI, OR1K_INSN_L_ROR
|
||||
, OR1K_INSN_L_RORI, OR1K_INSN_L_AND, OR1K_INSN_L_OR, OR1K_INSN_L_XOR
|
||||
, OR1K_INSN_L_ADD, OR1K_INSN_L_SUB, OR1K_INSN_L_ADDC, OR1K_INSN_L_MUL
|
||||
, OR1K_INSN_L_MULU, OR1K_INSN_L_DIV, OR1K_INSN_L_DIVU, OR1K_INSN_L_FF1
|
||||
, OR1K_INSN_L_FL1, OR1K_INSN_L_ANDI, OR1K_INSN_L_ORI, OR1K_INSN_L_XORI
|
||||
, OR1K_INSN_L_ADDI, OR1K_INSN_L_ADDIC, OR1K_INSN_L_MULI, OR1K_INSN_L_EXTHS
|
||||
, OR1K_INSN_L_EXTBS, OR1K_INSN_L_EXTHZ, OR1K_INSN_L_EXTBZ, OR1K_INSN_L_EXTWS
|
||||
, OR1K_INSN_L_EXTWZ, OR1K_INSN_L_CMOV, OR1K_INSN_L_SFGTS, OR1K_INSN_L_SFGTSI
|
||||
, OR1K_INSN_L_SFGTU, OR1K_INSN_L_SFGTUI, OR1K_INSN_L_SFGES, OR1K_INSN_L_SFGESI
|
||||
, OR1K_INSN_L_SFGEU, OR1K_INSN_L_SFGEUI, OR1K_INSN_L_SFLTS, OR1K_INSN_L_SFLTSI
|
||||
, OR1K_INSN_L_SFLTU, OR1K_INSN_L_SFLTUI, OR1K_INSN_L_SFLES, OR1K_INSN_L_SFLESI
|
||||
, OR1K_INSN_L_SFLEU, OR1K_INSN_L_SFLEUI, OR1K_INSN_L_SFEQ, OR1K_INSN_L_SFEQI
|
||||
, OR1K_INSN_L_SFNE, OR1K_INSN_L_SFNEI, OR1K_INSN_L_MAC, OR1K_INSN_L_MSB
|
||||
, OR1K_INSN_L_MACI, OR1K_INSN_L_CUST1, OR1K_INSN_L_CUST2, OR1K_INSN_L_CUST3
|
||||
, OR1K_INSN_L_CUST4, OR1K_INSN_L_CUST5, OR1K_INSN_L_CUST6, OR1K_INSN_L_CUST7
|
||||
, OR1K_INSN_L_CUST8, OR1K_INSN_LF_ADD_S, OR1K_INSN_LF_ADD_D, OR1K_INSN_LF_SUB_S
|
||||
, OR1K_INSN_LF_SUB_D, OR1K_INSN_LF_MUL_S, OR1K_INSN_LF_MUL_D, OR1K_INSN_LF_DIV_S
|
||||
, OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_REM_S, OR1K_INSN_LF_REM_D, OR1K_INSN_LF_ITOF_S
|
||||
, OR1K_INSN_LF_ITOF_D, OR1K_INSN_LF_FTOI_S, OR1K_INSN_LF_FTOI_D, OR1K_INSN_LF_EQ_S
|
||||
, OR1K_INSN_LF_EQ_D, OR1K_INSN_LF_NE_S, OR1K_INSN_LF_NE_D, OR1K_INSN_LF_GE_S
|
||||
, OR1K_INSN_LF_GE_D, OR1K_INSN_LF_GT_S, OR1K_INSN_LF_GT_D, OR1K_INSN_LF_LT_S
|
||||
, OR1K_INSN_LF_LT_D, OR1K_INSN_LF_LE_S, OR1K_INSN_LF_LE_D, OR1K_INSN_LF_MADD_S
|
||||
, OR1K_INSN_LF_MADD_D, OR1K_INSN_LF_CUST1_S, OR1K_INSN_LF_CUST1_D
|
||||
, OR1K_INSN_L_LWZ, OR1K_INSN_L_LWS, OR1K_INSN_L_LWA, OR1K_INSN_L_LBZ
|
||||
, OR1K_INSN_L_LBS, OR1K_INSN_L_LHZ, OR1K_INSN_L_LHS, OR1K_INSN_L_SW
|
||||
, OR1K_INSN_L_SB, OR1K_INSN_L_SH, OR1K_INSN_L_SWA, OR1K_INSN_L_SLL
|
||||
, OR1K_INSN_L_SLLI, OR1K_INSN_L_SRL, OR1K_INSN_L_SRLI, OR1K_INSN_L_SRA
|
||||
, OR1K_INSN_L_SRAI, OR1K_INSN_L_ROR, OR1K_INSN_L_RORI, OR1K_INSN_L_AND
|
||||
, OR1K_INSN_L_OR, OR1K_INSN_L_XOR, OR1K_INSN_L_ADD, OR1K_INSN_L_SUB
|
||||
, OR1K_INSN_L_ADDC, OR1K_INSN_L_MUL, OR1K_INSN_L_MULU, OR1K_INSN_L_DIV
|
||||
, OR1K_INSN_L_DIVU, OR1K_INSN_L_FF1, OR1K_INSN_L_FL1, OR1K_INSN_L_ANDI
|
||||
, OR1K_INSN_L_ORI, OR1K_INSN_L_XORI, OR1K_INSN_L_ADDI, OR1K_INSN_L_ADDIC
|
||||
, OR1K_INSN_L_MULI, OR1K_INSN_L_EXTHS, OR1K_INSN_L_EXTBS, OR1K_INSN_L_EXTHZ
|
||||
, OR1K_INSN_L_EXTBZ, OR1K_INSN_L_EXTWS, OR1K_INSN_L_EXTWZ, OR1K_INSN_L_CMOV
|
||||
, OR1K_INSN_L_SFGTS, OR1K_INSN_L_SFGTSI, OR1K_INSN_L_SFGTU, OR1K_INSN_L_SFGTUI
|
||||
, OR1K_INSN_L_SFGES, OR1K_INSN_L_SFGESI, OR1K_INSN_L_SFGEU, OR1K_INSN_L_SFGEUI
|
||||
, OR1K_INSN_L_SFLTS, OR1K_INSN_L_SFLTSI, OR1K_INSN_L_SFLTU, OR1K_INSN_L_SFLTUI
|
||||
, OR1K_INSN_L_SFLES, OR1K_INSN_L_SFLESI, OR1K_INSN_L_SFLEU, OR1K_INSN_L_SFLEUI
|
||||
, OR1K_INSN_L_SFEQ, OR1K_INSN_L_SFEQI, OR1K_INSN_L_SFNE, OR1K_INSN_L_SFNEI
|
||||
, OR1K_INSN_L_MAC, OR1K_INSN_L_MSB, OR1K_INSN_L_MACI, OR1K_INSN_L_CUST1
|
||||
, OR1K_INSN_L_CUST2, OR1K_INSN_L_CUST3, OR1K_INSN_L_CUST4, OR1K_INSN_L_CUST5
|
||||
, OR1K_INSN_L_CUST6, OR1K_INSN_L_CUST7, OR1K_INSN_L_CUST8, OR1K_INSN_LF_ADD_S
|
||||
, OR1K_INSN_LF_ADD_D, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D, OR1K_INSN_LF_MUL_S
|
||||
, OR1K_INSN_LF_MUL_D, OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_REM_S
|
||||
, OR1K_INSN_LF_REM_D, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D, OR1K_INSN_LF_FTOI_S
|
||||
, OR1K_INSN_LF_FTOI_D, OR1K_INSN_LF_EQ_S, OR1K_INSN_LF_EQ_D, OR1K_INSN_LF_NE_S
|
||||
, OR1K_INSN_LF_NE_D, OR1K_INSN_LF_GE_S, OR1K_INSN_LF_GE_D, OR1K_INSN_LF_GT_S
|
||||
, OR1K_INSN_LF_GT_D, OR1K_INSN_LF_LT_S, OR1K_INSN_LF_LT_D, OR1K_INSN_LF_LE_S
|
||||
, OR1K_INSN_LF_LE_D, OR1K_INSN_LF_MADD_S, OR1K_INSN_LF_MADD_D, OR1K_INSN_LF_CUST1_S
|
||||
, OR1K_INSN_LF_CUST1_D
|
||||
} CGEN_INSN_TYPE;
|
||||
|
||||
/* Index of `invalid' insn place holder. */
|
||||
|
||||
@ -140,6 +140,16 @@ static const CGEN_OPINST sfmt_l_lws_ops[] ATTRIBUTE_UNUSED = {
|
||||
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
||||
};
|
||||
|
||||
static const CGEN_OPINST sfmt_l_lwa_ops[] ATTRIBUTE_UNUSED = {
|
||||
{ INPUT, "h_memory_USI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 },
|
||||
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
||||
{ INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
|
||||
{ OUTPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
|
||||
{ OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 },
|
||||
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
||||
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
||||
};
|
||||
|
||||
static const CGEN_OPINST sfmt_l_lbz_ops[] ATTRIBUTE_UNUSED = {
|
||||
{ INPUT, "h_memory_UQI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_1", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 },
|
||||
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
||||
@ -173,26 +183,45 @@ static const CGEN_OPINST sfmt_l_lhs_ops[] ATTRIBUTE_UNUSED = {
|
||||
};
|
||||
|
||||
static const CGEN_OPINST sfmt_l_sw_ops[] ATTRIBUTE_UNUSED = {
|
||||
{ INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
|
||||
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
||||
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
||||
{ INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
|
||||
{ OUTPUT, "h_memory_USI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_split_4", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 },
|
||||
{ OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
|
||||
{ OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 },
|
||||
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
||||
};
|
||||
|
||||
static const CGEN_OPINST sfmt_l_sb_ops[] ATTRIBUTE_UNUSED = {
|
||||
{ INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
|
||||
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
||||
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
||||
{ INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
|
||||
{ OUTPUT, "h_memory_UQI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_split_1", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 },
|
||||
{ OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
|
||||
{ OUTPUT, "h_memory_UQI_addr", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 },
|
||||
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
||||
};
|
||||
|
||||
static const CGEN_OPINST sfmt_l_sh_ops[] ATTRIBUTE_UNUSED = {
|
||||
{ INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
|
||||
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
||||
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
||||
{ INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
|
||||
{ OUTPUT, "h_memory_UHI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_split_2", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 },
|
||||
{ OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
|
||||
{ OUTPUT, "h_memory_UHI_addr", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 },
|
||||
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
||||
};
|
||||
|
||||
static const CGEN_OPINST sfmt_l_swa_ops[] ATTRIBUTE_UNUSED = {
|
||||
{ INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
|
||||
{ INPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 },
|
||||
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
||||
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, COND_REF },
|
||||
{ INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
|
||||
{ INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
|
||||
{ OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 },
|
||||
{ OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, COND_REF },
|
||||
{ OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
|
||||
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
||||
};
|
||||
|
||||
@ -439,6 +468,7 @@ static const CGEN_OPINST *or1k_cgen_opinst_table[MAX_INSNS] = {
|
||||
& sfmt_l_mtspr_ops[0],
|
||||
& sfmt_l_lwz_ops[0],
|
||||
& sfmt_l_lws_ops[0],
|
||||
& sfmt_l_lwa_ops[0],
|
||||
& sfmt_l_lbz_ops[0],
|
||||
& sfmt_l_lbs_ops[0],
|
||||
& sfmt_l_lhz_ops[0],
|
||||
@ -446,6 +476,7 @@ static const CGEN_OPINST *or1k_cgen_opinst_table[MAX_INSNS] = {
|
||||
& sfmt_l_sw_ops[0],
|
||||
& sfmt_l_sb_ops[0],
|
||||
& sfmt_l_sh_ops[0],
|
||||
& sfmt_l_swa_ops[0],
|
||||
& sfmt_l_sll_ops[0],
|
||||
& sfmt_l_slli_ops[0],
|
||||
& sfmt_l_sll_ops[0],
|
||||
|
||||
Reference in New Issue
Block a user