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Add support for the LMBD (left-most bit detect) instruction to the PRU assembler.

Browse Source 
include	* opcode/pru.h: Add LMBD (left-most bit detect) opcode index
opcodes * pru-opc.c: Add opcode description for LMBD (left-most bit detect)
gas 	* testsuite/gas/pru/misc.s: Add tests for lmbd (left-most bit detect)
 	* testsuite/gas/pru/misc.d: Add tests for lmbd (left-most bit
This commit is contained in:
Spencer E. Olson
2020-11-09 12:41:09 +00:00
committed by Nick Clifton
parent 4a3e3e2282
commit 9372689d72
8 changed files with 65 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
gas/ChangeLog
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@ -1,3 +1,9 @@
2020-11-09 Spencer E. Olson <olsonse@umich.edu>
* testsuite/gas/pru/misc.s: Add tests for lmbd (left-most bit
detect).
* testsuite/gas/pru/misc.d: Update expected disassembly.
2020-11-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* config/tc-aarch64.c: Fix comment.

3
gas/testsuite/gas/pru/misc.d
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@ -9,3 +9,6 @@ Disassembly of section .text:
0+0000 <[^>]*> 2a000000 halt
0+0004 <[^>]*> 3e800000 slp 1
0+0008 <[^>]*> 3e000000 slp 0
0+000c <[^>]*> 2701e1e0 lmbd r0, r1, 1
0+0010 <[^>]*> 2700e100 lmbd r0.b0, r1, 0
0+0014 <[^>]*> 2642e1e0 lmbd r0, r1, sp.b2

3
gas/testsuite/gas/pru/misc.s
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@ -4,3 +4,6 @@ foo:
halt
slp 1
slp 0
lmbd r0, r1, 0x1
lmbd r0.b0, r1, 0x0
lmbd r0, r1, r2.b2

24
gas/write.c
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@ -771,6 +771,22 @@ resolve_reloc_expr_symbols (void)
}
}
static bfd_boolean
is_dwo_section (asection *sec)
{
const char *name;
int len;
if (sec == NULL || (name = bfd_section_name (sec)) == NULL)
return FALSE;
len = strlen (name);
if (len < 5)
return FALSE;
return strncmp (name + len - 4, ".dwo", 4) == 0;
}
/* This pass over fixups decides whether symbols can be replaced with
section symbols. */
@ -899,6 +915,14 @@ adjust_reloc_syms (bfd *abfd ATTRIBUTE_UNUSED,
#endif
}
/* PR 26841: DWO sections are not supposed to have relocations. */
if (is_dwo_section (sec) && seginfo->fix_root != NULL)
{
as_bad (_("DWO section '%s' contains unresolved expressions - this is not allowed"),
bfd_section_name (sec));
seginfo->fix_root = NULL; /* FIXME: Memory leak ? */
}
dump_section_relocs (abfd, sec, stderr);
}

4
include/ChangeLog
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@ -1,3 +1,7 @@
2020-11-09 Spencer E. Olson <olsonse@umich.edu>
* opcode/pru.h: Add LMBD (left-most bit detect) opcode index.
2020-11-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add new operand AARCH64_OPND_Rt_LS64.

34
include/opcode/pru.h
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@ -44,25 +44,27 @@ enum overflow_type
no_overflow
};
enum opcode_format_type {
opcode_format1,
opcode_format2ab,
opcode_format2abl,
opcode_format2c,
opcode_format2de,
opcode_format45,
opcode_format6
enum opcode_format_type
{
opcode_format1,
opcode_format2ab,
opcode_format2abl,
opcode_format2c,
opcode_format2de,
opcode_format45,
opcode_format6
};
/* Opcode ID listing. Used for indexing by the simulator. */
enum pru_instr_type {
prui_add, prui_adc, prui_sub, prui_suc, prui_lsl, prui_lsr, prui_rsb,
prui_rsc, prui_and, prui_or, prui_xor, prui_min, prui_max, prui_clr,
prui_set, prui_not, prui_jmp, prui_jal, prui_ldi, prui_halt, prui_slp,
prui_xin, prui_xout, prui_xchg, prui_sxin, prui_sxout, prui_sxchg,
prui_loop, prui_iloop, prui_qbgt, prui_qbge, prui_qblt, prui_qble,
prui_qbeq, prui_qbne, prui_qba, prui_qbbs, prui_qbbc, prui_lbbo,
prui_sbbo, prui_lbco, prui_sbco
enum pru_instr_type
{
prui_add, prui_adc, prui_sub, prui_suc, prui_lsl, prui_lsr, prui_rsb,
prui_rsc, prui_and, prui_or, prui_xor, prui_min, prui_max, prui_clr,
prui_set, prui_not, prui_jmp, prui_jal, prui_ldi, prui_lmbd,
prui_halt, prui_slp, prui_xin, prui_xout, prui_xchg, prui_sxin,
prui_sxout, prui_sxchg, prui_loop, prui_iloop, prui_qbgt, prui_qbge,
prui_qblt, prui_qble, prui_qbeq, prui_qbne, prui_qba, prui_qbbs,
prui_qbbc, prui_lbbo, prui_sbbo, prui_lbco, prui_sbco
};
/* This structure holds information for a particular instruction.

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2020-11-09 Spencer E. Olson <olsonse@umich.edu>
* pru-opc.c: Add opcode description for LMBD (left-most bit
detect).
2020-11-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add ACCDATA_EL1 system register

2
opcodes/pru-opc.c
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@ -121,6 +121,8 @@ const struct pru_opcode pru_opcodes[] =
OP_MATCH_JAL, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, unsigned_immed16_overflow},
{ "ldi", prui_ldi, "d,W",
OP_MATCH_LDI, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, unsigned_immed16_overflow},
{ "lmbd", prui_lmbd, "d,s,b",
OP_MATCH_LMBD, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, unsigned_immed8_overflow},
{ "halt", prui_halt, "",
OP_MATCH_HALT, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, no_overflow},
{ "slp", prui_slp, "w",