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Only generate VMOV.I64 instructions for loading constant floating point values if this instruction is supported by the currently selected fpu.

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PR target/2006764
	* config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64
	instruction if supported by the currently selected fpu variant.
	* testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR.
	* testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.
This commit is contained in:
Chua Zheng Leong
2016-05-25 13:09:51 +01:00
committed by Nick Clifton
parent 2bbad2ea11
commit 934c263269
4 changed files with 14 additions and 3 deletions
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8
gas/ChangeLog
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@ -1,3 +1,11 @@
2016-05-25 Chua Zheng Leong <chuazl@comp.nus.edu.sg>
PR target/2006764
* config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64
instruction if supported by the currently selected fpu variant.
* testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR.
* testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.
2016-05-24 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_fix_adjustable): Also return 0 for

2
gas/config/tc-arm.c
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@ -8000,7 +8000,7 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
return TRUE;
}
}
else if (t == CONST_VEC)
else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
{
int op = 0;
unsigned immbits = 0;

1
gas/testsuite/gas/arm/vfpv3-ldr_immediate.d
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@ -32,4 +32,5 @@ Disassembly of section \.text:
0[0-9a-fx]+ .*(00000000|40400000) .*
0[0-9a-fx]+ .*(40400000|00000000) .*
0[0-9a-fx]+ .*42000000 .*
0[0-9a-fx]+ .*ed1fbb01 vldr d11, \[pc, #-4\].*
#pass

4
gas/testsuite/gas/arm/vfpv3-ldr_immediate.s
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@ -42,5 +42,7 @@
vldr s0,=0x42000000
.pool
nop
# PR 20067
FLDD D11, =0
.pool