gas/

* config/tc-mips.c (can_swap_branch_p): Exclude microMIPS
	variant frags too.

	gas/testsuite/
	* gas/mips/relax-swap3.d: New test.
	* gas/mips/mips16@relax-swap3.d: Likewise.
	* gas/mips/micromips@relax-swap3.d: Likewise.
	* gas/mips/relax-swap3.s: New test source.
	* gas/mips/mips.exp: Run the new tests.

gas/ChangeLog

@@ -1,3 +1,8 @@
+2011-11-14  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* config/tc-mips.c (can_swap_branch_p): Exclude microMIPS
+	variant frags too.
+
 2011-11-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
 	* config/tc-arm.c (arm_cpus): Add cortex-a7 entry.

gas/config/tc-mips.c

@@ -3728,9 +3728,8 @@ can_swap_branch_p (struct mips_cl_insn *ip)
 
   /* If the previous instruction is in a variant frag other than this
      branch's one, we cannot do the swap.  This does not apply to
-     MIPS16/microMIPS code, which uses variant frags for different
+     MIPS16 code, which uses variant frags for different purposes.  */
-     purposes.  */
+  if (!mips_opts.mips16
-  if (!HAVE_CODE_COMPRESSION
       && history[0].frag
       && history[0].frag->fr_type == rs_machine_dependent)
     return FALSE;

gas/testsuite/ChangeLog

@@ -1,3 +1,11 @@
+2011-11-14  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* gas/mips/relax-swap3.d: New test.
+	* gas/mips/mips16@relax-swap3.d: Likewise.
+	* gas/mips/micromips@relax-swap3.d: Likewise.
+	* gas/mips/relax-swap3.s: New test source.
+	* gas/mips/mips.exp: Run the new tests.
+
 2011-11-02  Nick Clifton  <nickc@redhat.com>
 
 	* gas/arm/pic.d: Update expected output.

gas/testsuite/gas/mips/micromips@relax-swap3.d

@@ -0,0 +1,22 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS relaxed macro with branch swapping
+#as: -32
+#source: relax-swap3.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 41a2 0000 	lui	v0,0x0
+[ 	]*[0-9a-f]+: R_MICROMIPS_HI16	bar
+[0-9a-f]+ <[^>]*> 3042 0000 	addiu	v0,v0,0
+[ 	]*[0-9a-f]+: R_MICROMIPS_LO16	bar
+[0-9a-f]+ <[^>]*> 4583      	jr	v1
+[0-9a-f]+ <[^>]*> 0c00      	nop
+[0-9a-f]+ <[^>]*> 41a2 0000 	lui	v0,0x0
+[ 	]*[0-9a-f]+: R_MICROMIPS_HI16	bar
+[0-9a-f]+ <[^>]*> 3042 0000 	addiu	v0,v0,0
+[ 	]*[0-9a-f]+: R_MICROMIPS_LO16	bar
+[0-9a-f]+ <[^>]*> 8dff      	beqz	v1,[0-9a-f]+ <[^>]*>
+[ 	]*[0-9a-f]+: R_MICROMIPS_PC7_S1	.*
+[0-9a-f]+ <[^>]*> 0c00      	nop
+	\.\.\.

gas/testsuite/gas/mips/mips.exp

@@ -749,6 +749,7 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "relax-swap1-mips1"
     run_dump_test "relax-swap1-mips2"
     run_dump_test "relax-swap2"
+    run_dump_test_arches "relax-swap3"	[mips_arch_list_all]
     run_list_test_arches "relax-bposge" "-mdsp -relax-branch" \
 					[mips_arch_list_matching mips64r2 \
 					    !micromips]

gas/testsuite/gas/mips/mips16@relax-swap3.d

@@ -0,0 +1,15 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS relaxed macro with branch swapping
+#as: -32
+#source: relax-swap3.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0a00      	la	v0,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> eb00      	jr	v1
+[0-9a-f]+ <[^>]*> 6500      	nop
+[0-9a-f]+ <[^>]*> f7ff 0a1c 	la	v0,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 2300      	beqz	v1,[0-9a-f]+ <[^>]*>
+	\.\.\.
+#pass

gas/testsuite/gas/mips/relax-swap3.d

@@ -0,0 +1,21 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS relaxed macro with branch swapping
+#as: -32
+#source: relax-swap3.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 3c020000 	lui	v0,0x0
+[ 	]*[0-9a-f]+: R_MIPS_HI16	bar
+[0-9a-f]+ <[^>]*> 24420000 	addiu	v0,v0,0
+[ 	]*[0-9a-f]+: R_MIPS_LO16	bar
+[0-9a-f]+ <[^>]*> 00600008 	jr	v1
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 3c020000 	lui	v0,0x0
+[ 	]*[0-9a-f]+: R_MIPS_HI16	bar
+[0-9a-f]+ <[^>]*> 24420000 	addiu	v0,v0,0
+[ 	]*[0-9a-f]+: R_MIPS_LO16	bar
+[0-9a-f]+ <[^>]*> 10600001 	beqz	v1,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 	nop
+	\.\.\.

gas/testsuite/gas/mips/relax-swap3.s

@@ -0,0 +1,14 @@
+# Source file used to check the lack of branch swapping with a relaxed macro.
+
+	.text
+foo:
+	la	$2, bar
+	jr	$3
+
+	la	$2, bar
+	beqz	$3, 0f
+0:
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align	2
+	.space	8