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opcodes/

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* sparc-opc.c (sparc_opcodes): Fix random instruction to write
	to a float instead of an integer register.

gas/testsuite/

	* gas/sparc/hpcvis3.s: Update to use float reg for random insn.
	* gas/sparc/hpcvis3.d: Likewise.
This commit is contained in:
David S. Miller
2011-09-27 04:30:32 +00:00
parent 79df06c40d
commit 92a7795b59
5 changed files with 13 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
gas/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2011-09-27 David S. Miller <davem@davemloft.net>
* gas/sparc/hpcvis3.s: Update to use float reg for random insn.
* gas/sparc/hpcvis3.d: Likewise.
2011-09-26 David S. Miller <davem@davemloft.net> 2011-09-26 David S. Miller <davem@davemloft.net>
* gas/sparc/ima.d: New test. * gas/sparc/ima.d: New test.

2
gas/testsuite/gas/sparc/hpcvis3.d
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@ -41,7 +41,7 @@ Disassembly of section .text:
7c: 95 f9 11 c6 fnumaddd %f4, %f6, %f8, %f10 7c: 95 f9 11 c6 fnumaddd %f4, %f6, %f8, %f10
80: 8f b1 42 26 addxc %g5, %g6, %g7 80: 8f b1 42 26 addxc %g5, %g6, %g7
84: 97 b2 42 6a addxccc %o1, %o2, %o3 84: 97 b2 42 6a addxccc %o1, %o2, %o3
88: 99 b0 02 a0 random %o4 88: 8d b0 02 a0 random %f6
8c: 9f b3 42 ce umulxhi %o5, %sp, %o7 8c: 9f b3 42 ce umulxhi %o5, %sp, %o7
90: b5 b0 02 f9 lzd %i1, %i2 90: b5 b0 02 f9 lzd %i1, %i2
94: 81 b0 03 7b cmask8 %i3 94: 81 b0 03 7b cmask8 %i3

2
gas/testsuite/gas/sparc/hpcvis3.s
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@ -34,7 +34,7 @@
fnumaddd %f4, %f6, %f8, %f10 fnumaddd %f4, %f6, %f8, %f10
addxc %g5, %g6, %g7 addxc %g5, %g6, %g7
addxccc %o1, %o2, %o3 addxccc %o1, %o2, %o3
random %o4 random %f6
umulxhi %o5, %o6, %o7 umulxhi %o5, %o6, %o7
lzd %i1, %i2 lzd %i1, %i2
cmask8 %i3 cmask8 %i3

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2011-09-27 David S. Miller <davem@davemloft.net>
* sparc-opc.c (sparc_opcodes): Fix random instruction to write
to a float instead of an integer register.
2011-09-26 David S. Miller <davem@davemloft.net> 2011-09-26 David S. Miller <davem@davemloft.net>
* sparc-opc.c (sparc_opcodes): Add integer multiply-add * sparc-opc.c (sparc_opcodes): Add integer multiply-add

2
opcodes/sparc-opc.c
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@ -1869,7 +1869,7 @@ SLCBCC("cbnefr", 15),
{ "fnumaddd", F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT|F_FJFMAU, v9b }, { "fnumaddd", F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT|F_FJFMAU, v9b },
{ "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", F_VIS3, v9b }, { "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", F_VIS3, v9b },
{ "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", F_VIS3, v9b }, { "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", F_VIS3, v9b },
{ "random", F3F(2, 0x36, 0x015), F3F(~2, ~0x36, ~0x015), "d", F_RANDOM, v9b }, { "random", F3F(2, 0x36, 0x015), F3F(~2, ~0x36, ~0x015), "H", F_FLOAT|F_RANDOM, v9b },
{ "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", F_VIS3, v9b }, { "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", F_VIS3, v9b },
{ "lzd", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", F_VIS3, v9b }, { "lzd", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", F_VIS3, v9b },
{ "cmask8", F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", F_VIS3, v9b }, { "cmask8", F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", F_VIS3, v9b },