espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-30 00:52:16 +08:00
Code Issues Packages Projects Releases Wiki Activity

2013-11-19 Catherine Moore <clm@codesourcery.com>

Browse Source 
* micromips-opc.c (LM): Define.
	(micromips_opcodes): Add LM to load instructions.
	* mips-opc.c (prefe): Add LM attribute.
This commit is contained in:
Catherine Moore
2013-11-19 05:25:32 -08:00
parent a8d14a8892
commit 8f8c3854e0
3 changed files with 64 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2013-11-19 Catherine Moore <clm@codesourcery.com>
* micromips-opc.c (LM): Define.
(micromips_opcodes): Add LM to load instructions.
* mips-opc.c (prefe): Add LM attribute.
2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com> 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
Revert Revert

113
opcodes/micromips-opc.c
View File

@ -200,6 +200,7 @@ decode_micromips_operand (const char *p)
#define CBD INSN_COND_BRANCH_DELAY #define CBD INSN_COND_BRANCH_DELAY
#define NODS INSN_NO_DELAY_SLOT #define NODS INSN_NO_DELAY_SLOT
#define TRAP INSN_NO_DELAY_SLOT #define TRAP INSN_NO_DELAY_SLOT
#define LM INSN_LOAD_MEMORY
#define SM INSN_STORE_MEMORY #define SM INSN_STORE_MEMORY
#define BD16 INSN2_BRANCH_DELAY_16BIT /* Used in pinfo2. */ #define BD16 INSN2_BRANCH_DELAY_16BIT /* Used in pinfo2. */
#define BD32 INSN2_BRANCH_DELAY_32BIT /* Used in pinfo2. */ #define BD32 INSN2_BRANCH_DELAY_32BIT /* Used in pinfo2. */
@ -282,9 +283,9 @@ const struct mips_opcode micromips_opcodes[] =
them first. The assemblers uses a hash table based on the them first. The assemblers uses a hash table based on the
instruction name anyhow. */ instruction name anyhow. */
/* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */ /* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */
{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_3, 0, I1, 0, 0 }, {"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_3|LM, 0, I1, 0, 0 },
{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1, 0, 0 }, {"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1, 0, 0 },
{"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_2|RD_3|FP_S, 0, I1, 0, 0 }, {"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_2|RD_3|FP_S|LM, 0, I1, 0, 0 },
{"nop", "", 0x0c00, 0xffff, 0, INSN2_ALIAS, I1, 0, 0 }, {"nop", "", 0x0c00, 0xffff, 0, INSN2_ALIAS, I1, 0, 0 },
{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */
{"ssnop", "", 0x00000800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ {"ssnop", "", 0x00000800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */
@ -314,7 +315,7 @@ const struct mips_opcode micromips_opcodes[] =
{"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, {"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, {"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
{"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, {"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, RD_3|SM|NODS, 0, 0, MC, 0 }, {"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, RD_3|LM|SM|NODS, 0, 0, MC, 0 },
{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC, 0 }, {"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC, 0 },
{"add", "d,v,t", 0x00000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, {"add", "d,v,t", 0x00000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, 0 }, {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, 0 },
@ -346,7 +347,7 @@ const struct mips_opcode micromips_opcodes[] =
{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1, 0, 0 }, {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1, 0, 0 },
{"andi", "md,mc,mC", 0x2c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, {"andi", "md,mc,mC", 0x2c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 },
{"andi", "t,r,i", 0xd0000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, {"andi", "t,r,i", 0xd0000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 },
{"aset", "\\,~(b)", 0x20003000, 0xff00f000, RD_3|SM|NODS, 0, 0, MC, 0 }, {"aset", "\\,~(b)", 0x20003000, 0xff00f000, RD_3|LM|SM|NODS, 0, 0, MC, 0 },
{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC, 0 }, {"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC, 0 },
/* b is at the top of the table. */ /* b is at the top of the table. */
/* bal is at the top of the table. */ /* bal is at the top of the table. */
@ -741,78 +742,78 @@ const struct mips_opcode micromips_opcodes[] =
{"jals", "a", 0x74000000, 0xfc000000, WR_31|UBD, BD16, I1, 0, 0 }, {"jals", "a", 0x74000000, 0xfc000000, WR_31|UBD, BD16, I1, 0, 0 },
{"jalx", "+i", 0xf0000000, 0xfc000000, WR_31|UBD, BD32, I1, 0, 0 }, {"jalx", "+i", 0xf0000000, 0xfc000000, WR_31|UBD, BD32, I1, 0, 0 },
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 }, {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lb", "t,o(b)", 0x1c000000, 0xfc000000, WR_1|RD_3, 0, I1, 0, 0 }, {"lb", "t,o(b)", 0x1c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1, 0, 0 }, {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lbu", "md,mG(ml)", 0x0800, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, {"lbu", "md,mG(ml)", 0x0800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lbu", "t,o(b)", 0x14000000, 0xfc000000, WR_1|RD_3, 0, I1, 0, 0 }, {"lbu", "t,o(b)", 0x14000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1, 0, 0 }, {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1, 0, 0 }, {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1, 0, 0 },
/* The macro has to be first to handle o32 correctly. */ /* The macro has to be first to handle o32 correctly. */
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 },
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3, 0, I3, 0, 0 }, {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 },
{"ldc1", "T,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D, 0, I1, 0, 0 }, {"ldc1", "T,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 },
{"ldc1", "E,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D, 0, I1, 0, 0 }, {"ldc1", "E,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 },
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
{"ldc2", "E,~(b)", 0x20002000, 0xfc00f000, RD_3|WR_CC, 0, I1, 0, 0 }, {"ldc2", "E,~(b)", 0x20002000, 0xfc00f000, RD_3|WR_CC|LM, 0, I1, 0, 0 },
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I1, 0, 0 }, {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I1, 0, 0 },
{"l.d", "T,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D, 0, I1, 0, 0 }, /* ldc1 */ {"l.d", "T,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 }, /* ldc1 */
{"l.d", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, {"l.d", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
{"ldl", "t,~(b)", 0x60004000, 0xfc00f000, WR_1|RD_3, 0, I3, 0, 0 }, {"ldl", "t,~(b)", 0x60004000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 },
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, 0 }, {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, 0 },
{"ldm", "n,~(b)", 0x20007000, 0xfc00f000, RD_3, 0, I3, 0, 0 }, {"ldm", "n,~(b)", 0x20007000, 0xfc00f000, RD_3|LM, 0, I3, 0, 0 },
{"ldm", "n,A(b)", 0, (int) M_LDM_AB, INSN_MACRO, 0, I3, 0, 0 }, {"ldm", "n,A(b)", 0, (int) M_LDM_AB, INSN_MACRO, 0, I3, 0, 0 },
{"ldp", "t,~(b)", 0x20004000, 0xfc00f000, WR_1|RD_3, 0, I3, 0, 0 }, {"ldp", "t,~(b)", 0x20004000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 },
{"ldp", "t,A(b)", 0, (int) M_LDP_AB, INSN_MACRO, 0, I3, 0, 0 }, {"ldp", "t,A(b)", 0, (int) M_LDP_AB, INSN_MACRO, 0, I3, 0, 0 },
{"ldr", "t,~(b)", 0x60005000, 0xfc00f000, WR_1|RD_3, 0, I3, 0, 0 }, {"ldr", "t,~(b)", 0x60005000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 },
{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3, 0, 0 }, {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3, 0, 0 },
{"ldxc1", "D,t(b)", 0x540000c8, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, {"ldxc1", "D,t(b)", 0x540000c8, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D|LM, 0, I1, 0, 0 },
{"lh", "t,o(b)", 0x3c000000, 0xfc000000, WR_1|RD_3, 0, I1, 0, 0 }, {"lh", "t,o(b)", 0x3c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1, 0, 0 }, {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lhu", "md,mH(ml)", 0x2800, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, {"lhu", "md,mH(ml)", 0x2800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lhu", "t,o(b)", 0x34000000, 0xfc000000, WR_1|RD_3, 0, I1, 0, 0 }, {"lhu", "t,o(b)", 0x34000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1, 0, 0 }, {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1, 0, 0 },
/* li is at the start of the table. */ /* li is at the start of the table. */
{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
{"ll", "t,~(b)", 0x60003000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, 0 }, {"ll", "t,~(b)", 0x60003000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I1, 0, 0 }, {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lld", "t,~(b)", 0x60007000, 0xfc00f000, WR_1|RD_3, 0, I3, 0, 0 }, {"lld", "t,~(b)", 0x60007000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 },
{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, 0 }, {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, 0 },
{"lui", "s,u", 0x41a00000, 0xffe00000, WR_1, 0, I1, 0, 0 }, {"lui", "s,u", 0x41a00000, 0xffe00000, WR_1, 0, I1, 0, 0 },
{"luxc1", "D,t(b)", 0x54000148, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, {"luxc1", "D,t(b)", 0x54000148, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D|LM, 0, I1, 0, 0 },
{"lw", "md,mJ(ml)", 0x6800, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, {"lw", "md,mJ(ml)", 0x6800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lw", "mp,mU(ms)", 0x4800, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, /* lwsp */ {"lw", "mp,mU(ms)", 0x4800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* lwsp */
{"lw", "md,mA(ma)", 0x6400, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, /* lwgp */ {"lw", "md,mA(ma)", 0x6400, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* lwgp */
{"lw", "t,o(b)", 0xfc000000, 0xfc000000, WR_1|RD_3, 0, I1, 0, 0 }, {"lw", "t,o(b)", 0xfc000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1, 0, 0 }, {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lwc1", "T,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S, 0, I1, 0, 0 }, {"lwc1", "T,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM, 0, I1, 0, 0 },
{"lwc1", "E,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S, 0, I1, 0, 0 }, {"lwc1", "E,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM, 0, I1, 0, 0 },
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
{"lwc2", "E,~(b)", 0x20000000, 0xfc00f000, RD_3|WR_CC, 0, I1, 0, 0 }, {"lwc2", "E,~(b)", 0x20000000, 0xfc00f000, RD_3|WR_CC|LM, 0, I1, 0, 0 },
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, 0 }, {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, 0 },
{"l.s", "T,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S, 0, I1, 0, 0 }, /* lwc1 */ {"l.s", "T,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM, 0, I1, 0, 0 }, /* lwc1 */
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
{"lwl", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, 0 }, {"lwl", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 }, {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lcache", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, 0 }, /* same */ {"lcache", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* same */
{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 }, {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lwm", "mN,mJ(ms)", 0x4500, 0xffc0, RD_3|NODS, 0, I1, 0, 0 }, {"lwm", "mN,mJ(ms)", 0x4500, 0xffc0, RD_3|NODS|LM, 0, I1, 0, 0 },
{"lwm", "n,~(b)", 0x20005000, 0xfc00f000, RD_3|NODS, 0, I1, 0, 0 }, {"lwm", "n,~(b)", 0x20005000, 0xfc00f000, RD_3|NODS|LM, 0, I1, 0, 0 },
{"lwm", "n,A(b)", 0, (int) M_LWM_AB, INSN_MACRO, 0, I1, 0, 0 }, {"lwm", "n,A(b)", 0, (int) M_LWM_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lwp", "t,~(b)", 0x20001000, 0xfc00f000, WR_1|RD_3|NODS, 0, I1, 0, 0 }, {"lwp", "t,~(b)", 0x20001000, 0xfc00f000, WR_1|RD_3|NODS|LM, 0, I1, 0, 0 },
{"lwp", "t,A(b)", 0, (int) M_LWP_AB, INSN_MACRO, 0, I1, 0, 0 }, {"lwp", "t,A(b)", 0, (int) M_LWP_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lwr", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, 0 }, {"lwr", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 }, {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lwu", "t,~(b)", 0x6000e000, 0xfc00f000, WR_1|RD_3, 0, I3, 0, 0 }, {"lwu", "t,~(b)", 0x6000e000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 },
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3, 0, 0 }, {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3, 0, 0 },
{"lwxc1", "D,t(b)", 0x54000048, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, {"lwxc1", "D,t(b)", 0x54000048, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S|LM, 0, I1, 0, 0 },
{"flush", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, 0 }, /* same */ {"flush", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, 0 }, /* same */
{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 }, {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, {"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, I1, 0, 0 },
{"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 }, {"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 },
{"madd", "7,s,t", 0x00000abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"madd", "7,s,t", 0x00000abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 },
{"madd.d", "D,R,S,T", 0x54000009, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, {"madd.d", "D,R,S,T", 0x54000009, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 },
@ -1131,21 +1132,21 @@ const struct mips_opcode micromips_opcodes[] =
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1, 0, 0 }, {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1, 0, 0 },
{"xori", "t,r,i", 0x70000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, {"xori", "t,r,i", 0x70000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 },
/* microMIPS Enhanced VA Scheme */ /* microMIPS Enhanced VA Scheme */
{"lbue", "t,+j(b)", 0x60006000, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, {"lbue", "t,+j(b)", 0x60006000, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"lhue", "t,+j(b)", 0x60006200, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, {"lhue", "t,+j(b)", 0x60006200, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"lbe", "t,+j(b)", 0x60006800, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, {"lbe", "t,+j(b)", 0x60006800, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"lhe", "t,+j(b)", 0x60006a00, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, {"lhe", "t,+j(b)", 0x60006a00, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"lle", "t,+j(b)", 0x60006c00, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, {"lle", "t,+j(b)", 0x60006c00, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"lwe", "t,+j(b)", 0x60006e00, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, {"lwe", "t,+j(b)", 0x60006e00, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"lwle", "t,+j(b)", 0x60006400, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, {"lwle", "t,+j(b)", 0x60006400, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"lwre", "t,+j(b)", 0x60006600, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, {"lwre", "t,+j(b)", 0x60006600, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"sbe", "t,+j(b)", 0x6000a800, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 }, {"sbe", "t,+j(b)", 0x6000a800, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 },
{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA, 0 },
@ -1161,7 +1162,7 @@ const struct mips_opcode micromips_opcodes[] =
{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"cachee", "k,+j(b)", 0x6000a600, 0xfc00fe00, RD_3, 0, 0, EVA, 0 }, {"cachee", "k,+j(b)", 0x6000a600, 0xfc00fe00, RD_3, 0, 0, EVA, 0 },
{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 }, {"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 },
{"prefe", "k,+j(b)", 0x6000a400, 0xfc00fe00, RD_3, 0, 0, EVA, 0 }, {"prefe", "k,+j(b)", 0x6000a400, 0xfc00fe00, RD_3|LM, 0, 0, EVA, 0 },
{"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA, 0 },
/* MIPS DSP ASE. */ /* MIPS DSP ASE. */
{"absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, {"absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 },
@ -1205,9 +1206,9 @@ const struct mips_opcode micromips_opcodes[] =
{"extrv.w", "t,7,s", 0x00000ebc, 0xfc003fff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, {"extrv.w", "t,7,s", 0x00000ebc, 0xfc003fff, WR_1|RD_3|RD_a, 0, 0, D32, 0 },
{"extr.w", "t,7,6", 0x00000e7c, 0xfc003fff, WR_1|RD_a, 0, 0, D32, 0 }, {"extr.w", "t,7,6", 0x00000e7c, 0xfc003fff, WR_1|RD_a, 0, 0, D32, 0 },
{"insv", "t,s", 0x0000413c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, {"insv", "t,s", 0x0000413c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 },
{"lbux", "d,t(b)", 0x00000225, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, {"lbux", "d,t(b)", 0x00000225, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, D32, 0 },
{"lhx", "d,t(b)", 0x00000165, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, {"lhx", "d,t(b)", 0x00000165, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, D32, 0 },
{"lwx", "d,t(b)", 0x000001a5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, {"lwx", "d,t(b)", 0x000001a5, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, D32, 0 },
{"maq_sa.w.phl", "7,s,t", 0x00003a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"maq_sa.w.phl", "7,s,t", 0x00003a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 },
{"maq_sa.w.phr", "7,s,t", 0x00002a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"maq_sa.w.phr", "7,s,t", 0x00002a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 },
{"maq_s.w.phl", "7,s,t", 0x00001a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"maq_s.w.phl", "7,s,t", 0x00001a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 },
@ -1478,10 +1479,10 @@ const struct mips_opcode micromips_opcodes[] =
{"clei_u.h", "+d,+e,+$", 0x5aa00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, {"clei_u.h", "+d,+e,+$", 0x5aa00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
{"clei_u.w", "+d,+e,+$", 0x5ac00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, {"clei_u.w", "+d,+e,+$", 0x5ac00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
{"clei_u.d", "+d,+e,+$", 0x5ae00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, {"clei_u.d", "+d,+e,+$", 0x5ae00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
{"ld.b", "+d,+T(d)", 0x58000007, 0xfc00003f, WR_1|RD_3, 0, 0, MSA, 0 }, {"ld.b", "+d,+T(d)", 0x58000007, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 },
{"ld.h", "+d,+U(d)", 0x58000017, 0xfc00003f, WR_1|RD_3, 0, 0, MSA, 0 }, {"ld.h", "+d,+U(d)", 0x58000017, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 },
{"ld.w", "+d,+V(d)", 0x58000027, 0xfc00003f, WR_1|RD_3, 0, 0, MSA, 0 }, {"ld.w", "+d,+V(d)", 0x58000027, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 },
{"ld.d", "+d,+W(d)", 0x58000037, 0xfc00003f, WR_1|RD_3, 0, 0, MSA, 0 }, {"ld.d", "+d,+W(d)", 0x58000037, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 },
{"st.b", "+d,+T(d)", 0x5800000f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, {"st.b", "+d,+T(d)", 0x5800000f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 },
{"st.h", "+d,+U(d)", 0x5800001f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, {"st.h", "+d,+U(d)", 0x5800001f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 },
{"st.w", "+d,+V(d)", 0x5800002f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, {"st.w", "+d,+V(d)", 0x5800002f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 },

2
opcodes/mips-opc.c
View File

@ -2568,7 +2568,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"cachee", "k,+j(b)", 0x7c00001b, 0xfc00007f, RD_3, 0, 0, EVA, 0 }, {"cachee", "k,+j(b)", 0x7c00001b, 0xfc00007f, RD_3, 0, 0, EVA, 0 },
{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 }, {"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 },
{"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_3, 0, 0, EVA, 0 }, {"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_3|LM, 0, 0, EVA, 0 },
{"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA, 0 },
/* MSA Extension. */ /* MSA Extension. */
{"sll.b", "+d,+e,+h", 0x7800000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"sll.b", "+d,+e,+h", 0x7800000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },