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Reverted writes_to_pc() back to old version of code until PC operands are
supported by cgen.
This commit is contained in:
@ -5,14 +5,15 @@ Fri Feb 13 16:41:42 1998 Ian Lance Taylor <ian@cygnus.com>
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* doc/Makefile.am (AUTOMAKE_OPTIONS): Define.
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* doc/Makefile.am (AUTOMAKE_OPTIONS): Define.
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* doc/Makefile.in: Rebuild.
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* doc/Makefile.in: Rebuild.
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start-sanitize-m32rx
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Fri Feb 13 09:57:11 1998 Nick Clifton <nickc@cygnus.com>
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Fri Feb 13 09:57:11 1998 Nick Clifton <nickc@cygnus.com>
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* config/tc-m32r.c (first_writes_to_seconds_operands): New
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* config/tc-m32r.c (first_writes_to_seconds_operands): New
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function. Replaces get_src_reg(), check_for_side_effects(),
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function. Replaces get_src_reg(), check_for_side_effects(),
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reads_from_src_reg(). Uses new insn operand features of cgen.
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reads_from_src_reg(). Uses new insn operand features of cgen.
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(writes_to_pc): New function.
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(writes_to_pc): New function., but with new code suppressed for now.
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(md_assemble): Call first_writes_to_seconds_operands().
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(md_assemble): Call first_writes_to_seconds_operands().
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end-sanitize-m32rx
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Fri Feb 13 00:47:44 1998 Ian Lance Taylor <ian@cygnus.com>
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Fri Feb 13 00:47:44 1998 Ian Lance Taylor <ian@cygnus.com>
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* config/tc-mips.c (macro_build): Handle operand type 'C'.
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* config/tc-mips.c (macro_build): Handle operand type 'C'.
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@ -432,8 +432,9 @@ static int
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writes_to_pc (a)
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writes_to_pc (a)
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m32r_insn * a;
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m32r_insn * a;
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{
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{
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#if 0
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const CGEN_OPERAND_INSTANCE * a_operands;
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const CGEN_OPERAND_INSTANCE * a_operands;
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for (a_operands = CGEN_INSN_OPERANDS (a->insn);
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for (a_operands = CGEN_INSN_OPERANDS (a->insn);
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CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END;
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CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END;
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a_operands ++)
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a_operands ++)
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@ -442,7 +443,11 @@ writes_to_pc (a)
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&& CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC)
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&& CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC)
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return 1;
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return 1;
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}
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}
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#else
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if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI)
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|| CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI))
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return 1;
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#endif
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return 0;
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return 0;
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}
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}
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@ -70,7 +70,7 @@ There are several warning and error messages that can be produced by
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@table @code
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@table @code
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@item output of first instruction is the same as the input of second instruction - is this intentional ?
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@item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?
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This message is only produced if warnings for explicit parallel
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This message is only produced if warnings for explicit parallel
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conflicts have been enabled. It indicates that the assembler has
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conflicts have been enabled. It indicates that the assembler has
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encountered a parallel instruction in which the destination register of
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encountered a parallel instruction in which the destination register of
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@ -79,7 +79,7 @@ instruction. For example in this code fragment
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@samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the
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@samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the
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move instruction and the input to the neg instruction.
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move instruction and the input to the neg instruction.
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@item output of second instruction is the same as the input of first instruction - is this intentional ?
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@item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?
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This message is only produced if warnings for explicit parallel
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This message is only produced if warnings for explicit parallel
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conflicts have been enabled. It indicates that the assembler has
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conflicts have been enabled. It indicates that the assembler has
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encountered a parallel instruction in which the destination register of
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encountered a parallel instruction in which the destination register of
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@ -109,31 +109,14 @@ executed in parallel.
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This message is produced when the assembler encounters a parallel
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This message is produced when the assembler encounters a parallel
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instruction whoes components both use the same execution pipeline.
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instruction whoes components both use the same execution pipeline.
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@item Both instructions write to the link register
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This message is produced when the assembler encounters a parallel
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instruction whoes components both write to the link register, one of
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them as a side effect. For example this code fragment will produce this
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message: @samp{jl r0 || mv r14, r1}
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@item Destination of first instruction written to by side effect of second instruction.
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This message is produced when the assembler encounters a parallel
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instruction whoes right hand component has a side effect which modifes a
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register used as the destination by the left hand component. For
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example this code fragment will produce this message:
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@samp{mv r1, r2 || ld r0, @@r1+}
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@item Destination of second instruction written to by side effect of first instruction.
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This message is produced when the assembler encounters a parallel
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instruction whoes left hand component has a side effect which modifes a
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register used as the destination by the right hand component. For
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example this code fragment will produce this message:
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@samp{st r2, @@-r1 || mv r1, r3}
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@item Instructions write to the same destination register.
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@item Instructions write to the same destination register.
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This message is produced when the assembler encounters a parallel
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This message is produced when the assembler encounters a parallel
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instruction where both components attempt to modify the same register.
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instruction where both components attempt to modify the same register.
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For example this code fragment will produce this message:
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For example these code fragments will produce this message:
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@samp{mv r1, r2 || neg r1, r3}
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@samp{mv r1, r2 || neg r1, r3}
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@samp{jl r0 || mv r14, r1}
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@samp{st r2, @@-r1 || mv r1, r3}
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@samp{mv r1, r2 || ld r0, @@r1+}
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@end table
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@end table
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@c end-sanitize-m32rx
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@c end-sanitize-m32rx
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