mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-06-24 04:00:07 +08:00
x86: convert broadcast insn attribute to boolean
The (only) valid broadcast type for an insn can be inferred from other information.
This commit is contained in:
Jan Beulich
@ -1,3 +1,12 @@
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2018-03-28 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (struct Broadcast_Operation): Adjust comment.
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(check_VecOperands): Re-write broadcast validation code.
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(check_VecOperations): Replace BROADCAST_1TO* uses.
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* testsuite/gas/i386/inval-avx512f.s: Add various broadcast
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cases.
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* testsuite/gas/i386/inval-avx512f.l: Adjust expectations.
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2018-03-28 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (process_suffix): Check .todword/.toqword
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@ -225,7 +225,7 @@ static struct Mask_Operation mask_op;
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broadcast factor. */
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struct Broadcast_Operation
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{
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/* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
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/* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
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int type;
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/* Index of broadcasted operand. */
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@ -5048,13 +5048,13 @@ check_VecOperands (const insn_template *t)
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to the memory operand. */
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if (i.broadcast)
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{
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int broadcasted_opnd_size;
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i386_operand_type type, overlap;
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/* Check if specified broadcast is supported in this instruction,
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and it's applied to memory operand of DWORD or QWORD type,
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depending on VecESize. */
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op = i.broadcast->operand;
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if (i.broadcast->type != t->opcode_modifier.broadcast
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if (!t->opcode_modifier.broadcast
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|| !i.types[op].bitfield.mem
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|| (t->opcode_modifier.vecesize == 0
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&& !i.types[op].bitfield.dword
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@ -5062,29 +5062,49 @@ check_VecOperands (const insn_template *t)
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|| (t->opcode_modifier.vecesize == 1
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&& !i.types[op].bitfield.qword
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&& !i.types[op].bitfield.unspecified))
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goto bad_broadcast;
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broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
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if (i.broadcast->type == BROADCAST_1TO16)
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broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
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else if (i.broadcast->type == BROADCAST_1TO8)
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broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
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else if (i.broadcast->type == BROADCAST_1TO4)
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broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
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else if (i.broadcast->type == BROADCAST_1TO2)
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broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
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else
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goto bad_broadcast;
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if ((broadcasted_opnd_size == 256
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&& !t->operand_types[op].bitfield.ymmword)
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|| (broadcasted_opnd_size == 512
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&& !t->operand_types[op].bitfield.zmmword))
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{
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bad_broadcast:
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i.error = unsupported_broadcast;
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return 1;
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}
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operand_type_set (&type, 0);
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switch ((t->opcode_modifier.vecesize ? 8 : 4) * i.broadcast->type)
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{
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case 8:
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type.bitfield.qword = 1;
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break;
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case 16:
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type.bitfield.xmmword = 1;
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break;
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case 32:
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type.bitfield.ymmword = 1;
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break;
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case 64:
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type.bitfield.zmmword = 1;
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break;
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default:
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goto bad_broadcast;
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}
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overlap = operand_type_and (type, t->operand_types[op]);
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if (operand_type_all_zero (&overlap))
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goto bad_broadcast;
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if (t->opcode_modifier.checkregsize)
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{
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unsigned int j;
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for (j = 0; j < i.operands; ++j)
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{
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if (j != op
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&& !operand_type_register_match(i.types[j],
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t->operand_types[j],
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type,
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t->operand_types[op]))
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goto bad_broadcast;
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}
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}
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}
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/* If broadcast is supported in this instruction, we need to check if
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operand of one-element size isn't specified without broadcast. */
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@ -8445,15 +8465,15 @@ check_VecOperations (char *op_string, char *op_end)
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op_string += 3;
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if (*op_string == '8')
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bcst_type = BROADCAST_1TO8;
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bcst_type = 8;
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else if (*op_string == '4')
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bcst_type = BROADCAST_1TO4;
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bcst_type = 4;
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else if (*op_string == '2')
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bcst_type = BROADCAST_1TO2;
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bcst_type = 2;
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else if (*op_string == '1'
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&& *(op_string+1) == '6')
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{
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bcst_type = BROADCAST_1TO16;
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bcst_type = 16;
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op_string++;
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}
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else
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@ -40,6 +40,66 @@
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.*:54: Error: .*
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.*:57: Error: .*
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.*:58: Error: .*
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.*:61: Error: .*vmovaps.*
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.*:62: Error: .*vmovaps.*
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.*:63: Error: .*vmovaps.*
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.*:64: Error: .*vmovaps.*
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.*:66: Error: .*vcvtps2pd.*
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.*:67: Error: .*vcvtps2pd.*
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.*:69: Error: .*vcvtps2pd.*
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.*:71: Error: .*vcvtps2pd.*
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.*:73: Error: .*vcvtps2pd.*
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.*:74: Error: .*vcvtps2pd.*
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.*:77: Error: .*vcvtps2pd.*
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.*:78: Error: .*vcvtps2pd.*
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.*:79: Error: .*vcvtps2pd.*
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.*:81: Error: .*vaddps.*
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.*:82: Error: .*vaddps.*
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.*:83: Error: .*vaddps.*
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.*:86: Error: .*vaddps.*
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.*:87: Error: .*vaddps.*
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.*:89: Error: .*vaddps.*
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.*:91: Error: .*vaddps.*
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.*:93: Error: .*vaddps.*
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.*:94: Error: .*vaddps.*
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.*:96: Error: .*vaddpd.*
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.*:97: Error: .*vaddpd.*
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.*:99: Error: .*vaddpd.*
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.*:101: Error: .*vaddpd.*
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.*:103: Error: .*vaddpd.*
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.*:104: Error: .*vaddpd.*
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.*:107: Error: .*vaddpd.*
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.*:108: Error: .*vaddpd.*
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.*:109: Error: .*vaddpd.*
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.*:112: Error: .*vcvtps2pd.*
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.*:113: Error: .*vcvtps2pd.*
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.*:117: Error: .*vcvtps2pd.*
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.*:118: Error: .*vcvtps2pd.*
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.*:119: Error: .*vcvtps2pd.*
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.*:121: Error: .*vaddps.*
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.*:122: Error: .*vaddps.*
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.*:123: Error: .*vaddps.*
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.*:125: Error: .*vaddps.*
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.*:126: Error: .*vaddps.*
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.*:127: Error: .*vaddps.*
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.*:130: Error: .*vaddps.*
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.*:131: Error: .*vaddps.*
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.*:133: Error: .*vaddps.*
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.*:135: Error: .*vaddps.*
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.*:137: Error: .*vaddps.*
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.*:138: Error: .*vaddps.*
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.*:140: Error: .*vaddpd.*
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.*:141: Error: .*vaddpd.*
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.*:142: Error: .*vaddpd.*
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.*:144: Error: .*vaddpd.*
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.*:145: Error: .*vaddpd.*
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.*:147: Error: .*vaddpd.*
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.*:149: Error: .*vaddpd.*
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.*:151: Error: .*vaddpd.*
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.*:152: Error: .*vaddpd.*
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.*:155: Error: .*vaddpd.*
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.*:156: Error: .*vaddpd.*
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.*:157: Error: .*vaddpd.*
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GAS LISTING .*
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@ -103,3 +163,122 @@ GAS LISTING .*
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GAS LISTING .*
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#...
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[ ]*58[ ]+vaddps zmm2\{z\}, zmm1, zmm0
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[ ]*59[ ]*
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[ ]*60[ ]+\.att_syntax prefix
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[ ]*61[ ]+vmovaps \(%eax\)\{1to2\}, %zmm1
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[ ]*62[ ]+vmovaps \(%eax\)\{1to4\}, %zmm1
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[ ]*63[ ]+vmovaps \(%eax\)\{1to8\}, %zmm1
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[ ]*64[ ]+vmovaps \(%eax\)\{1to16\}, %zmm1
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[ ]*65[ ]*
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[ ]*66[ ]+vcvtps2pd \(%eax\)\{1to2\}, %zmm1
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[ ]*67[ ]+vcvtps2pd \(%eax\)\{1to4\}, %zmm1
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[ ]*68 \?\?\?\? 62F17C58[ ]+vcvtps2pd \(%eax\)\{1to8\}, %zmm1
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[ ]*68[ ]+5A08
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[ ]*69[ ]+vcvtps2pd \(%eax\)\{1to16\}, %zmm1
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[ ]*70[ ]*
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[ ]*71[ ]+vcvtps2pd \(%eax\)\{1to2\}, %ymm1
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[ ]*72 \?\?\?\? 62F17C38[ ]+vcvtps2pd \(%eax\)\{1to4\}, %ymm1
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[ ]*72[ ]+5A08
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[ ]*73[ ]+vcvtps2pd \(%eax\)\{1to8\}, %ymm1
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[ ]*74[ ]+vcvtps2pd \(%eax\)\{1to16\}, %ymm1
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[ ]*75[ ]*
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[ ]*76 \?\?\?\? 62F17C18[ ]+vcvtps2pd \(%eax\)\{1to2\}, %xmm1
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[ ]*76[ ]+5A08
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[ ]*77[ ]+vcvtps2pd \(%eax\)\{1to4\}, %xmm1
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[ ]*78[ ]+vcvtps2pd \(%eax\)\{1to8\}, %xmm1
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[ ]*79[ ]+vcvtps2pd \(%eax\)\{1to16\}, %xmm1
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[ ]*80[ ]+
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[ ]*81[ ]+vaddps \(%eax\)\{1to2\}, %zmm1, %zmm2
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[ ]*82[ ]+vaddps \(%eax\)\{1to4\}, %zmm1, %zmm2
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[ ]*83[ ]+vaddps \(%eax\)\{1to8\}, %zmm1, %zmm2
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[ ]*84 \?\?\?\? 62F17458[ ]+vaddps \(%eax\)\{1to16\}, %zmm1, %zmm2
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[ ]*84[ ]+5810
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[ ]*85[ ]*
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[ ]*86[ ]+vaddps \(%eax\)\{1to2\}, %ymm1, %ymm2
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[ ]*87[ ]+vaddps \(%eax\)\{1to4\}, %ymm1, %ymm2
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[ ]*88 \?\?\?\? 62F17438[ ]+vaddps \(%eax\)\{1to8\}, %ymm1, %ymm2
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[ ]*88[ ]+5810
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[ ]*89[ ]+vaddps \(%eax\)\{1to16\}, %ymm1, %ymm2
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[ ]*90[ ]*
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[ ]*91[ ]+vaddps \(%eax\)\{1to2\}, %xmm1, %xmm2
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[ ]*92 \?\?\?\? 62F17418[ ]+vaddps \(%eax\)\{1to4\}, %xmm1, %xmm2
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[ ]*92[ ]+5810
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[ ]*93[ ]+vaddps \(%eax\)\{1to8\}, %xmm1, %xmm2
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[ ]*94[ ]+vaddps \(%eax\)\{1to16\}, %xmm1, %xmm2
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[ ]*95[ ]*
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[ ]*96[ ]+vaddpd \(%eax\)\{1to2\}, %zmm1, %zmm2
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[ ]*97[ ]+vaddpd \(%eax\)\{1to4\}, %zmm1, %zmm2
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[ ]*98 \?\?\?\? 62F1F558[ ]+vaddpd \(%eax\)\{1to8\}, %zmm1, %zmm2
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[ ]*98[ ]+5810
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[ ]*99[ ]+vaddpd \(%eax\)\{1to16\}, %zmm1, %zmm2
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[ ]*100[ ]*
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[ ]*101[ ]+vaddpd \(%eax\)\{1to2\}, %ymm1, %ymm2
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[ ]*102 \?\?\?\? 62F1F538[ ]+vaddpd \(%eax\)\{1to4\}, %ymm1, %ymm2
|
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[ ]*102[ ]+5810
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[ ]*103[ ]+vaddpd \(%eax\)\{1to8\}, %ymm1, %ymm2
|
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[ ]*104[ ]+vaddpd \(%eax\)\{1to16\}, %ymm1, %ymm2
|
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[ ]*105[ ]*
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[ ]*106 \?\?\?\? 62F1F518[ ]+vaddpd \(%eax\)\{1to2\}, %xmm1, %xmm2
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GAS LISTING .*
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#...
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[ ]*106[ ]+5810
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[ ]*107[ ]+vaddpd \(%eax\)\{1to4\}, %xmm1, %xmm2
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[ ]*108[ ]+vaddpd \(%eax\)\{1to8\}, %xmm1, %xmm2
|
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[ ]*109[ ]+vaddpd \(%eax\)\{1to16\}, %xmm1, %xmm2
|
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[ ]*110[ ]*
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[ ]*111[ ]+\.intel_syntax noprefix
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[ ]*112[ ]+vcvtps2pd zmm1, QWORD PTR \[eax\]
|
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[ ]*113[ ]+vcvtps2pd ymm1, QWORD PTR \[eax\]
|
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[ ]*114 \?\?\?\? C5F85A08[ ]+vcvtps2pd xmm1, QWORD PTR \[eax\]
|
||||
[ ]*115[ ]*
|
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[ ]*116 \?\?\?\? 62F17C18[ ]+vcvtps2pd xmm1, DWORD PTR \[eax\]\{1to2\}
|
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[ ]*116[ ]+5A08
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[ ]*117[ ]+vcvtps2pd xmm1, DWORD PTR \[eax\]\{1to4\}
|
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[ ]*118[ ]+vcvtps2pd xmm1, DWORD PTR \[eax\]\{1to8\}
|
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[ ]*119[ ]+vcvtps2pd xmm1, DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*120[ ]*
|
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[ ]*121[ ]+vaddps zmm2, zmm1, QWORD PTR \[eax\]
|
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[ ]*122[ ]+vaddps ymm2, ymm1, QWORD PTR \[eax\]
|
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[ ]*123[ ]+vaddps xmm2, xmm1, QWORD PTR \[eax\]
|
||||
[ ]*124[ ]*
|
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[ ]*125[ ]+vaddps zmm2, zmm1, DWORD PTR \[eax\]\{1to2\}
|
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[ ]*126[ ]+vaddps zmm2, zmm1, DWORD PTR \[eax\]\{1to4\}
|
||||
[ ]*127[ ]+vaddps zmm2, zmm1, DWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*128 \?\?\?\? 62F17458[ ]+vaddps zmm2, zmm1, DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*128[ ]+5810
|
||||
[ ]*129[ ]*
|
||||
[ ]*130[ ]+vaddps ymm2, ymm1, DWORD PTR \[eax\]\{1to2\}
|
||||
[ ]*131[ ]+vaddps ymm2, ymm1, DWORD PTR \[eax\]\{1to4\}
|
||||
[ ]*132 \?\?\?\? 62F17438[ ]+vaddps ymm2, ymm1, DWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*132[ ]+5810
|
||||
[ ]*133[ ]+vaddps ymm2, ymm1, DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*134[ ]*
|
||||
[ ]*135[ ]+vaddps xmm2, xmm1, DWORD PTR \[eax\]\{1to2\}
|
||||
[ ]*136 \?\?\?\? 62F17418[ ]+vaddps xmm2, xmm1, DWORD PTR \[eax\]\{1to4\}
|
||||
[ ]*136[ ]+5810
|
||||
[ ]*137[ ]+vaddps xmm2, xmm1, DWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*138[ ]+vaddps xmm2, xmm1, DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*139[ ]*
|
||||
[ ]*140[ ]+vaddpd zmm2, zmm1, DWORD PTR \[eax\]
|
||||
[ ]*141[ ]+vaddpd ymm2, ymm1, DWORD PTR \[eax\]
|
||||
[ ]*142[ ]+vaddpd xmm2, xmm1, DWORD PTR \[eax\]
|
||||
[ ]*143[ ]*
|
||||
[ ]*144[ ]+vaddpd zmm2, zmm1, QWORD PTR \[eax\]\{1to2\}
|
||||
[ ]*145[ ]+vaddpd zmm2, zmm1, QWORD PTR \[eax\]\{1to4\}
|
||||
[ ]*146 \?\?\?\? 62F1F558[ ]+vaddpd zmm2, zmm1, QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*146[ ]+5810
|
||||
[ ]*147[ ]+vaddpd zmm2, zmm1, QWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*148[ ]*
|
||||
[ ]*149[ ]+vaddpd ymm2, ymm1, QWORD PTR \[eax\]\{1to2\}
|
||||
[ ]*150 \?\?\?\? 62F1F538[ ]+vaddpd ymm2, ymm1, QWORD PTR \[eax\]\{1to4\}
|
||||
[ ]*150[ ]+5810
|
||||
[ ]*151[ ]+vaddpd ymm2, ymm1, QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*152[ ]+vaddpd ymm2, ymm1, QWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*153[ ]*
|
||||
[ ]*154 \?\?\?\? 62F1F518[ ]+vaddpd xmm2, xmm1, QWORD PTR \[eax\]\{1to2\}
|
||||
[ ]*154[ ]+5810
|
||||
[ ]*155[ ]+vaddpd xmm2, xmm1, QWORD PTR \[eax\]\{1to4\}
|
||||
GAS LISTING .*
|
||||
#...
|
||||
[ ]*156[ ]+vaddpd xmm2, xmm1, QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*157[ ]+vaddpd xmm2, xmm1, QWORD PTR \[eax\]\{1to16\}
|
||||
|
||||
@ -56,3 +56,102 @@ _start:
|
||||
.intel_syntax noprefix
|
||||
vaddps zmm2{ecx}, zmm1, zmm0
|
||||
vaddps zmm2{z}, zmm1, zmm0
|
||||
|
||||
.att_syntax prefix
|
||||
vmovaps (%eax){1to2}, %zmm1
|
||||
vmovaps (%eax){1to4}, %zmm1
|
||||
vmovaps (%eax){1to8}, %zmm1
|
||||
vmovaps (%eax){1to16}, %zmm1
|
||||
|
||||
vcvtps2pd (%eax){1to2}, %zmm1
|
||||
vcvtps2pd (%eax){1to4}, %zmm1
|
||||
vcvtps2pd (%eax){1to8}, %zmm1
|
||||
vcvtps2pd (%eax){1to16}, %zmm1
|
||||
|
||||
vcvtps2pd (%eax){1to2}, %ymm1
|
||||
vcvtps2pd (%eax){1to4}, %ymm1
|
||||
vcvtps2pd (%eax){1to8}, %ymm1
|
||||
vcvtps2pd (%eax){1to16}, %ymm1
|
||||
|
||||
vcvtps2pd (%eax){1to2}, %xmm1
|
||||
vcvtps2pd (%eax){1to4}, %xmm1
|
||||
vcvtps2pd (%eax){1to8}, %xmm1
|
||||
vcvtps2pd (%eax){1to16}, %xmm1
|
||||
|
||||
vaddps (%eax){1to2}, %zmm1, %zmm2
|
||||
vaddps (%eax){1to4}, %zmm1, %zmm2
|
||||
vaddps (%eax){1to8}, %zmm1, %zmm2
|
||||
vaddps (%eax){1to16}, %zmm1, %zmm2
|
||||
|
||||
vaddps (%eax){1to2}, %ymm1, %ymm2
|
||||
vaddps (%eax){1to4}, %ymm1, %ymm2
|
||||
vaddps (%eax){1to8}, %ymm1, %ymm2
|
||||
vaddps (%eax){1to16}, %ymm1, %ymm2
|
||||
|
||||
vaddps (%eax){1to2}, %xmm1, %xmm2
|
||||
vaddps (%eax){1to4}, %xmm1, %xmm2
|
||||
vaddps (%eax){1to8}, %xmm1, %xmm2
|
||||
vaddps (%eax){1to16}, %xmm1, %xmm2
|
||||
|
||||
vaddpd (%eax){1to2}, %zmm1, %zmm2
|
||||
vaddpd (%eax){1to4}, %zmm1, %zmm2
|
||||
vaddpd (%eax){1to8}, %zmm1, %zmm2
|
||||
vaddpd (%eax){1to16}, %zmm1, %zmm2
|
||||
|
||||
vaddpd (%eax){1to2}, %ymm1, %ymm2
|
||||
vaddpd (%eax){1to4}, %ymm1, %ymm2
|
||||
vaddpd (%eax){1to8}, %ymm1, %ymm2
|
||||
vaddpd (%eax){1to16}, %ymm1, %ymm2
|
||||
|
||||
vaddpd (%eax){1to2}, %xmm1, %xmm2
|
||||
vaddpd (%eax){1to4}, %xmm1, %xmm2
|
||||
vaddpd (%eax){1to8}, %xmm1, %xmm2
|
||||
vaddpd (%eax){1to16}, %xmm1, %xmm2
|
||||
|
||||
.intel_syntax noprefix
|
||||
vcvtps2pd zmm1, QWORD PTR [eax]
|
||||
vcvtps2pd ymm1, QWORD PTR [eax]
|
||||
vcvtps2pd xmm1, QWORD PTR [eax]
|
||||
|
||||
vcvtps2pd xmm1, DWORD PTR [eax]{1to2}
|
||||
vcvtps2pd xmm1, DWORD PTR [eax]{1to4}
|
||||
vcvtps2pd xmm1, DWORD PTR [eax]{1to8}
|
||||
vcvtps2pd xmm1, DWORD PTR [eax]{1to16}
|
||||
|
||||
vaddps zmm2, zmm1, QWORD PTR [eax]
|
||||
vaddps ymm2, ymm1, QWORD PTR [eax]
|
||||
vaddps xmm2, xmm1, QWORD PTR [eax]
|
||||
|
||||
vaddps zmm2, zmm1, DWORD PTR [eax]{1to2}
|
||||
vaddps zmm2, zmm1, DWORD PTR [eax]{1to4}
|
||||
vaddps zmm2, zmm1, DWORD PTR [eax]{1to8}
|
||||
vaddps zmm2, zmm1, DWORD PTR [eax]{1to16}
|
||||
|
||||
vaddps ymm2, ymm1, DWORD PTR [eax]{1to2}
|
||||
vaddps ymm2, ymm1, DWORD PTR [eax]{1to4}
|
||||
vaddps ymm2, ymm1, DWORD PTR [eax]{1to8}
|
||||
vaddps ymm2, ymm1, DWORD PTR [eax]{1to16}
|
||||
|
||||
vaddps xmm2, xmm1, DWORD PTR [eax]{1to2}
|
||||
vaddps xmm2, xmm1, DWORD PTR [eax]{1to4}
|
||||
vaddps xmm2, xmm1, DWORD PTR [eax]{1to8}
|
||||
vaddps xmm2, xmm1, DWORD PTR [eax]{1to16}
|
||||
|
||||
vaddpd zmm2, zmm1, DWORD PTR [eax]
|
||||
vaddpd ymm2, ymm1, DWORD PTR [eax]
|
||||
vaddpd xmm2, xmm1, DWORD PTR [eax]
|
||||
|
||||
vaddpd zmm2, zmm1, QWORD PTR [eax]{1to2}
|
||||
vaddpd zmm2, zmm1, QWORD PTR [eax]{1to4}
|
||||
vaddpd zmm2, zmm1, QWORD PTR [eax]{1to8}
|
||||
vaddpd zmm2, zmm1, QWORD PTR [eax]{1to16}
|
||||
|
||||
vaddpd ymm2, ymm1, QWORD PTR [eax]{1to2}
|
||||
vaddpd ymm2, ymm1, QWORD PTR [eax]{1to4}
|
||||
vaddpd ymm2, ymm1, QWORD PTR [eax]{1to8}
|
||||
vaddpd ymm2, ymm1, QWORD PTR [eax]{1to16}
|
||||
|
||||
vaddpd xmm2, xmm1, QWORD PTR [eax]{1to2}
|
||||
vaddpd xmm2, xmm1, QWORD PTR [eax]{1to4}
|
||||
vaddpd xmm2, xmm1, QWORD PTR [eax]{1to8}
|
||||
vaddpd xmm2, xmm1, QWORD PTR [eax]{1to16}
|
||||
|
||||
@ -1,3 +1,11 @@
|
||||
2018-03-28 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
|
||||
BROADCAST_1TO4, BROADCAST_1TO2): Delete.
|
||||
(struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
|
||||
* i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
|
||||
* i386-tlb.h: Re-generate.
|
||||
|
||||
2018-03-28 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
|
||||
|
||||
@ -572,16 +572,6 @@ enum
|
||||
*/
|
||||
VecESize,
|
||||
|
||||
/* Broadcast factor.
|
||||
0: No broadcast.
|
||||
1: 1to16 broadcast.
|
||||
2: 1to8 broadcast.
|
||||
*/
|
||||
#define NO_BROADCAST 0
|
||||
#define BROADCAST_1TO16 1
|
||||
#define BROADCAST_1TO8 2
|
||||
#define BROADCAST_1TO4 3
|
||||
#define BROADCAST_1TO2 4
|
||||
Broadcast,
|
||||
|
||||
/* Static rounding control is supported. */
|
||||
@ -672,7 +662,7 @@ typedef struct i386_opcode_modifier
|
||||
unsigned int evex:3;
|
||||
unsigned int masking:2;
|
||||
unsigned int vecesize:1;
|
||||
unsigned int broadcast:3;
|
||||
unsigned int broadcast:1;
|
||||
unsigned int staticrounding:1;
|
||||
unsigned int sae:1;
|
||||
unsigned int disp8memshift:3;
|
||||
|
||||
2108
opcodes/i386-opc.tbl
2108
opcodes/i386-opc.tbl
File diff suppressed because it is too large
Load Diff
1770
opcodes/i386-tbl.h
1770
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user